coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/qualcomm/sc7{1,2}80: Increase early stages size for clang
by Arthur Heymans (Code Review) 02 Oct '24

02 Oct '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80639?usp=email ) Change subject: soc/qualcomm/sc7{1,2}80: Increase early stages size for clang ...................................................................... soc/qualcomm/sc7{1,2}80: Increase early stages size for clang Clang builds slightly larger binaries so increase the section. The qcsdi is used for an external blob that is currently not in use so reducing the size is fine for now. Change-Id: Ide01233f209613678c5408f1afab19415c1071be Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80639 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index adc9a0b..9c500c2 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -23,7 +23,7 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 104K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 112K) REGION(qcsdi, 0x1469E000, 55K, 4K) REGION(modem_id, 0x146ABD00, 4, 4) SSRAM_END(0x146AE000) @@ -31,9 +31,9 @@ BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 83K, 4K) WATCHDOG_TOMBSTONE(0x14814FFC, 4) - BOOTBLOCK(0x14815000, 48K) - TPM_LOG(0x14821000, 2K) - PRERAM_CBFS_CACHE(0x14821800, 60K) + BOOTBLOCK(0x14815000, 52K) + TPM_LOG(0x14822000, 2K) + PRERAM_CBFS_CACHE(0x14822800, 56K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) TIMESTAMP(0x14838800, 1K) TTB(0x14839000, 56K) diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 231b9fe..b37b481 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -25,8 +25,8 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 104K) - REGION(qcsdi, 0x1469A000, 44K, 4K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 112K) + REGION(qcsdi, 0x1469C000, 39K + 256, 4K) REGION(modem_id, 0x146A5D00, 4, 4) SSRAM_END(0x146AB000) -- To view, visit https://review.coreboot.org/c/coreboot/+/80639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide01233f209613678c5408f1afab19415c1071be Gerrit-Change-Number: 80639 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelley Chen <shchen(a)google.com>

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[XS] Change in coreboot[main]: mb/google/byra/var/kinox: Add/update VBT files
by Yu-Ping Wu (Code Review) 02 Oct '24

02 Oct '24

Yu-Ping Wu has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83996?usp=email ) Change subject: mb/google/byra/var/kinox: Add/update VBT files ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > This CL breaks chromiumos as vbts are not installed the way this CL installed them, so the build bre […] Hmmm ... the copy-bot hashtag is supposed to be added for the downstream patch CL:5806924 instead of here. -- To view, visit https://review.coreboot.org/c/coreboot/+/83996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce Gerrit-Change-Number: 83996 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 06:18:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Anil Kumar K, Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 199: Code-Review-1 (3 comments) File src/mainboard/google/fatcat/Kconfig: https://review.coreboot.org/c/coreboot/+/83419/comment/5c1baf97_6ba57e47?us… : PS199, Line 20: PMC_IPC_ACPI_INTERFACE why are we dropping this now ? https://review.coreboot.org/c/coreboot/+/83419/comment/d9e2da3e_d586d7bd?us… : PS199, Line 23: SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 why are we dropping this now ? https://review.coreboot.org/c/coreboot/+/83419/comment/16ef87d8_4ee2e885?us… : PS199, Line 106: config OVERRIDE_DEVICETREE : default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" why are we dropping this now ? resulted in compilation error ``` In file included from src/mainboard/google/fatcat/variants/fatcat/variant.c:5: src/mainboard/google/fatcat/variants/fatcat/variant.c: In function 'get_wifi_sar_cbfs_filename': src/include/fw_config.h:41:23: error: 'FW_CONFIG_FIELD_WIFI_NAME' undeclared (first use in this function) 41 | .field_name = FW_CONFIG_FIELD_##__field##_NAME, \ | ^~~~~~~~~~~~~~~~ src/mainboard/google/fatcat/variants/fatcat/variant.c:10:48: note: in expansion of macro 'FW_CONFIG_FIELD' 10 | return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); | ^~~~~~~~~~~~~~~ src/include/fw_config.h:41:23: note: each undeclared identifier is reported only once for each function it appears in 41 | .field_name = FW_CONFIG_FIELD_##__field##_NAME, \ | ^~~~~~~~~~~~~~~~ src/mainboard/google/fatcat/variants/fatcat/variant.c:10:48: note: in expansion of macro 'FW_CONFIG_FIELD' 10 | return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); | ^~~~~~~~~~~~~~~ CC ramstage/lib/memchr.o src/include/fw_config.h:42:17: error: 'FW_CONFIG_FIELD_WIFI_MASK' undeclared (first use in this function) 42 | .mask = FW_CONFIG_FIELD_##__field##_MASK, \ | ^~~~~~~~~~~~~~~~ src/mainboard/google/fatcat/variants/fatcat/variant.c:10:48: note: in expansion of macro 'FW_CONFIG_FIELD' 10 | return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); | ^~~~~~~~~~~~~~~ src/mainboard/google/fatcat/variants/fatcat/variant.c:11:1: error: control reaches end of non-void function [-Werror=return-type] 11 | } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 199 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Oct 2024 05:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC721 codec
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Anil Kumar K, Karthik Ramasubramanian, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/84610?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC721 codec ...................................................................... Patch Set 1: (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/84610/comment/d43d4ebd_1a3cccf1?us… : PS1, Line 165: #if CONFIG(DRIVERS_SOUNDWIRE_ALC_BASE_7XX) : .name = "Realtek ALC 7 Series SoundWire Codec", can you please submit a separate code for this alone as base CL then add support for 721 codec ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1022ee91b16374d0d4d07e5198226595d61403a6 Gerrit-Change-Number: 84610 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 04:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 15: (2 comments) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/fd2a6b87_aebfcf30?us… : PS11, Line 250: static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, : const struct soc_intel_pantherlake_config *config) : { : const struct microcode *microcode; : size_t length; : : if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) : s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); : : if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) { : /* Locate microcode and pass to FSP-S for 2nd microcode loading */ : microcode = intel_microcode_find(); : if (!microcode) : return; : : length = get_microcode_size(microcode); : if (!length) : return; : : /* Update CPU Microcode patch base address/size */ : s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode; : s_cfg->MicrocodeRegionSize = (uint32_t)length; : } : } > > 1. USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI <— FSP runs coreboot APIs > > 2. USE_INTEL_FSP_MP_INIT <— FSP runs own APIs > > > > in case #2 , filling the CpuMpPpi UPD won't harm. > > That is simply not true. If `CpuMpPpi` is set while `USE_INTEL_FSP_MP_INIT=y` and `CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI=n` the FSP hit some exceptions inside coreboot MP functions because some initialization were not performed. If Is set to `NULL` which clearly is what is appropriate under this configuration when the CPU initialization execute just fine. > > > if you wish to use #2 (which we don't plan to use) then please select USE_INTEL_FSP_MP_INIT config. > > I do not plan on changing the default configuration, this is just about setting the UPD appropriately. updated code looks good to me https://review.coreboot.org/c/coreboot/+/84552/comment/18d7fd53_170d13d6?us… : PS11, Line 301: max_port = get_max_tcss_port(); : for (i = 0; i < max_port; i++) > There was no way I would introduce inconsistent code as I would have if I had followed your proposal so I created [84616: soc/intel/pantherlake: Remove soc_info.[hc] interface](https://review.coreboot.org/c/coreboot/+/84616) instead. Obviously, the CPU cycles saving is completely ridiculous can you please explain why this is "completely ridiculous" ? (ideally I would like to avoid making use of such a word while communicating to someone) Have you compared the assembly instruction between below codes (code 1 and code 2)? Code 1 ``` max_port = get_max_tcss_port(); for (i = 0; i < max_port; i++) if (config->tcss_ports[i].en ``` Code 2 ``` for (i = 0; i < MAX_TYPE_C_PORTS; i++) if (config->tcss_ports[i].en ``` here is the code analysis report Function call involved in code 1: get_max_tcss_port() - This involves a function call overhead (pushing arguments, jumping to the function, executing the function, returning the value). Code 2 is likely more optimized in terms of instruction count. Function calls generally involve more instructions than accessing a constant value. -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 15 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 04:42:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add GPIO settings
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Pranava Y N, Wonkyu Kim. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email ) Change subject: mb/google/fatcat: Add GPIO settings ...................................................................... Patch Set 22: (2 comments) File src/mainboard/google/fatcat/variants/fatcat/gpio.c: https://review.coreboot.org/c/coreboot/+/84405/comment/f273b6e4_72c3beab?us… : PS1, Line 440: /* GPP_C05: CRD1_PWREN */ > We will need fw_config for camera1 & 2. I created tables are ready in https://review.coreboot.org/c/coreboot/+/84408/19. can you please clarify what you mean by CAMERA 1 and CAMERA 2? are you referring to camera interface like MIPI vs USB here ? or UFC vs WFC? we would like to keep both UFC and WFC enabled but I agree with you that we need one more FW config to disable UFC/WFC interface for lab deployment. File src/mainboard/google/fatcat/variants/fatcat/gpio.c: https://review.coreboot.org/c/coreboot/+/84405/comment/7f23c6e0_778a46ee?us… : PS21, Line 253: overridden via fw_config > Subrata, How about changing to 'fw_config: <field name>'? Initially, I thought we wanted to remove those pads from the ramstage table and then found out that the pad needs to be in the table in order for fw_config to override. If the pad does not in the table, the override won't happen. I can also remove these additional comments entirely. In fact, it makes us easier since the pads including their comment are generated by a script. I mean, we don't need such commenting in this file -- To view, visit https://review.coreboot.org/c/coreboot/+/84405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Gerrit-Change-Number: 84405 Gerrit-PatchSet: 22 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 04:27:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Remove soc_info.[hc] interface
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84616?usp=email ) Change subject: soc/intel/pantherlake: Remove soc_info.[hc] interface ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6986 Gerrit-Change-Number: 84616 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 03:24:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Delete duplicated line
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84607?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Delete duplicated line ...................................................................... soc/intel/pantherlake: Delete duplicated line BUG=348678529 TEST=Build successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84607 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 4d5e178..2a7891b 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -261,7 +261,6 @@ const struct soc_intel_pantherlake_config *config) { m_cfg->TccActivationOffset = config->tcc_offset; - m_cfg->TccActivationOffset = config->tcc_offset; } static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/84607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Gerrit-Change-Number: 84607 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel: Deprecate `FSP_STATUS_GLOBAL_RESET` configs
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84540?usp=email ) Change subject: soc/intel: Deprecate `FSP_STATUS_GLOBAL_RESET` configs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica2faea5ff0dae50fa130cd891f06e5d94aed186 Gerrit-Change-Number: 84540 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel: Support interface-independent FSP reset status
by Subrata Banik (Code Review) 02 Oct '24

02 Oct '24

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84538?usp=email ) Change subject: soc/intel: Support interface-independent FSP reset status ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bcdd6d82c66318757032913c002aa67e6301ae6 Gerrit-Change-Number: 84538 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de>

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