coreboot-gerrit October 2024

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify GPIO for WWAN
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84611?usp=email ) Change subject: mb/google/brox/jubilant: Modify GPIO for WWAN ...................................................................... mb/google/brox/jubilant: Modify GPIO for WWAN The LTE module RW101R-GL provide a hardware pin to enable/disable WWAN RF function.The function is disabled in default and is controlled by the AT command.Therefore,set the WWAN_RF_DISABLE Pin to NC, and it has been pull-high by hardware desgin. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify the WWAN on/off function in OS. Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Kenneth Chan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c index aad759d..71c00ea 100644 --- a/src/mainboard/google/brox/variants/jubilant/gpio.c +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -12,8 +12,8 @@ PAD_CFG_GPI(GPP_E11, NONE, PLTRST), /* GPP_E17 : [NF2: THC0_SPI1_INT# NF6: USB_C_GPP_E17] ==> WWAN_CFG02 */ PAD_CFG_GPI(GPP_E17, NONE, PLTRST), - /* GPP_D7 : SRCCLKREQ2_L ==> WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO_LOCK(GPP_D7, 1, LOCK_CONFIG), + /* GPP_D7 : SRCCLKREQ2_L ==> WWAN_RF_DISABLE (Reserved) */ + PAD_NC_LOCK(GPP_D7, NONE, LOCK_CONFIG), /* GPP_D5 : SRCCLKREQ0_L ==> WWAN_SAR_ODL */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> WWAN_WLAN_COEX1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967 Gerrit-Change-Number: 84611 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/tpm: Remove unused 2nd argument in FUNC method
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84605?usp=email ) Change subject: drivers/tpm: Remove unused 2nd argument in FUNC method ...................................................................... drivers/tpm: Remove unused 2nd argument in FUNC method The method "FUNC" allows 1 argument, so remove the incorrectly referenced and unused second arguemnt. This fixes: ToInteger (Arg1, Local1) Error 6006 - ^ Method argument is not initialized (Arg1) Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/drivers/tpm/ppi.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Nicholas Sudsgaard: Looks good to me, approved build bot (Jenkins): Verified Michał Kopeć: Looks good to me, approved diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c index 2ce1d07..68923ea 100644 --- a/src/drivers/tpm/ppi.c +++ b/src/drivers/tpm/ppi.c @@ -634,7 +634,6 @@ acpigen_write_method_serialized("FUNC", 1); acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); - acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); acpigen_write_if(); acpigen_emit_byte(LGREATER_OP); acpigen_emit_byte(LOCAL0_OP); -- To view, visit https://review.coreboot.org/c/coreboot/+/84605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7 Gerrit-Change-Number: 84605 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84134?usp=email to look at the new patch set (#19). Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth ...................................................................... drivers/usb/acpi: Add AOLD Method for Intel Bluetooth Add AOLD Method, which simply returns an integer based on whether Audio Offload is enabled. Leave the existing control of Audio Offload in `soc/soc_chip.h`, and add second control in the USB ACPI `chip.h` which takes precedence if used. Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 84 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/84134/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/84134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Gerrit-Change-Number: 84134 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Maximilian Brune, Paul Menzel. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet ...................................................................... Patch Set 4: Code-Review+2 (2 comments) Patchset: PS4: apart from the open comment about the register names in the commit message, this looks god to me Commit Message: https://review.coreboot.org/c/coreboot/+/84574/comment/76fb6760_6df76bb5?us… : PS4, Line 9: MISC2/3 > 1/2 or is my math wrong? Otherwise the patch LGTM. yes, MISC1 and MISC2. those 4 registers are counted in a really weird way though: MISC, MISC0, MISC1 and MISC2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/rpl: Set the maximum C state to C6
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84623?usp=email ) Change subject: mb/starlabs/starbook/rpl: Set the maximum C state to C6 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49afff42762f2bd06c52512930e98e9fc1d03620 Gerrit-Change-Number: 84623 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:39:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Introduce MAX_C_STATE to control maximum state
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Introduce MAX_C_STATE to control maximum state ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:39:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superflous compiler argument
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84621?usp=email ) Change subject: soc/intel/alderlake: Remove superflous compiler argument ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:38:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:38:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix PEG0 IRQ routing
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84619?usp=email ) Change subject: soc/intel/alderlake: Fix PEG0 IRQ routing ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498 Gerrit-Change-Number: 84619 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:38:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/glinda/.../iomap.h: Update for glinda
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Maximilian Brune, Paul Menzel. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84380/comment/9f871d5c_222385eb?us… : PS4, Line 10: DMA4 apparently doesn't exist anymore so remove it. no; it's just not visible in the ppr version you have access to :( File src/soc/amd/glinda/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84380/comment/8cfc08fd_1fdb1b4c?us… : PS4, Line 35: #define APU_DMAC4_BASE 0xfedd0000 this is still there; just not visible in the non-internal ppr. also there's always one dmac per uart, so having UART4, but not DMAC4 doesn't seem right File src/soc/amd/glinda/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84380/comment/37ca20a1_11f4e8d3?us… : PS1, Line 33: #define APU_UART4_BASE 0xfedd1000 //TODO not in the table but used on actual schematics (does it exist or not?) > I was looking at table 147 in document 57254 (Rev 1.59) and I can't see UART4 there. […] please mention the name of the table; the table number isn't helpful for me, since i'm looking at the internal version and not the more or less redacted one which has other table numbers due to less things being visible. is that the "Address Space Mapping under APB BUS" table? if that table and the register descriptions disagree, i'd much rather trust the register descriptions than that table -- To view, visit https://review.coreboot.org/c/coreboot/+/84380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Gerrit-Change-Number: 84380 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 11:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit October 2024