coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

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2622 discussions

[XS] Change in coreboot[main]: soc/amd/glinda/.../iomap.h: Update for glinda
by Maximilian Brune (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Maximilian Brune, Paul Menzel. Hello Marshall Dawson, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84380?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ...................................................................... soc/amd/glinda/.../iomap.h: Update for glinda Remove TODO after checking the addresses are still valid. source: PPR 57254 Rev 1.59 Table "Address Space Mapping under APB BUS" Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/iomap.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/84380/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Gerrit-Change-Number: 84380 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84596?usp=email to look at the new patch set (#11). Change subject: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree ...................................................................... soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree Hook up CNVi Bluetooth UPDs to the devicetree, and set them to true so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/chipset.cb M src/soc/intel/cannonlake/chipset_pch_h.cb M src/soc/intel/cannonlake/fsp_params.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84596/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Gerrit-Change-Number: 84596 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: Update fsp submodule to upstream master
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Felix Singer. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84597?usp=email ) Change subject: Update fsp submodule to upstream master ...................................................................... Patch Set 2: (1 comment) File 3rdparty/fsp: https://review.coreboot.org/c/coreboot/+/84597/comment/023f12e2_8e9210d0?us… : PS1, Line 1: Subproject commit bb12f17b07700a40c0033da345eae0c1cd487b73 > The latest commit has a different ID 02b30da989444aa988ebb00c00c414bb662babd3 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib414495bd2b7e6fe363277bad1031e06ab8d503c Gerrit-Change-Number: 84597 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:05:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: Update fsp submodule to upstream master
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Sean Rhodes. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84597?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Update fsp submodule to upstream master ...................................................................... Update fsp submodule to upstream master Updating from commit id 68328e2: 2024-08-05 14:46:35 +0800 - (NEX ADL-PS IPU 2024.4 (5045_03) FSP) to commit id 02b30da: 2024-09-12 16:00:43 +0800 - (NEX RPL-P MR2 Hotfix (5134_03) FSP) This brings in 5 new commits: Update MemInfoHob.h Update MemInfoHob.h NEX AZB IPU 2025.1 (5363_00) FSP NEX RPL-S MR4/RPL-S Refresh MR2 Hotfix (5134_05) FSP NEX RPL-P MR2 Hotfix (5134_03) FSP Change-Id: Ib414495bd2b7e6fe363277bad1031e06ab8d503c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84597/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib414495bd2b7e6fe363277bad1031e06ab8d503c Gerrit-Change-Number: 84597 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
by Maximilian Brune (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84574/comment/1fd75ea9_541991cb?us… : PS4, Line 9: MISC2/3 > yes, MISC1 and MISC2. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:04:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
by Maximilian Brune (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Maximilian Brune, Paul Menzel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84574?usp=email to look at the new patch set (#5). Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet ...................................................................... soc/amd/.../amd_pci_int_defs.h: Update according to datasheet HPET and MISC1/2 and registers are used interchangeably in the datasheets. Add an alias to emphasise that they refer to the same. source: PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list" PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list" PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84574/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Correctly set Usb4CmMode
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77567?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Correctly set Usb4CmMode ...................................................................... soc/intel/meteorlake: Correctly set Usb4CmMode The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will timeout. TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567 Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Michał Kopeć: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Ronak Kanabar: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index bf1d9d5..702820a 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -442,6 +442,8 @@ if (is_dev_enabled(tcss_port_arr[i])) s_cfg->UsbTcPortEn |= BIT(i); } + + s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); } static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/77567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Gerrit-Change-Number: 77567 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Correctly set Usb4CmMode
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ravishankar Sarawadi, Subrata Banik, Tarun, Utkarsh H Patel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/77567?usp=email ) Change subject: soc/intel/meteorlake: Correctly set Usb4CmMode ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77567/comment/7dd65ac3_e2e272ab?us… : PS7, Line 11: mismatched. > Fits on the line above. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Gerrit-Change-Number: 77567 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 13:52:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Correctly set Usb4CmMode
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ravishankar Sarawadi, Sean Rhodes, Subrata Banik, Tarun, Utkarsh H Patel. Hello Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Martin L Roth, Michał Kopeć, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun, Tim Crawford, Utkarsh H Patel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77567?usp=email to look at the new patch set (#9). Change subject: soc/intel/meteorlake: Correctly set Usb4CmMode ...................................................................... soc/intel/meteorlake: Correctly set Usb4CmMode The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will timeout. TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/77567/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/77567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Gerrit-Change-Number: 77567 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84304?usp=email ) Change subject: soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources ...................................................................... soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources On GNR, there are CXL Type-3 memory windows covered under TOHM. The current 4GB to TOHM DRAM reporting doesn't work on GNR. Use MemoryMapDataHob to add high RAM resources as a generic mechanism for GNR and previous generation SoCs. TEST=Build and boot on intel/archercity CRB TEST=Build and boot on intel/beechnutcity CRB (with topic:"Xeon6-Basic-Boot") Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index be5b38f..c20e55f 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,21 +284,25 @@ mc_values[TOLM_REG]); LOG_RESOURCE("mmio_tolm", dev, res); - if (CONFIG(SOC_INTEL_HAS_CXL)) { - /* 4GiB -> CXL Memory */ - uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ - /* - * Memory layout when there is CXL HDM (Host-managed Device Memory): - * -------------- <- TOHM - * CXL memory regions (pds global variable records the base/size of them) - * Processor attached high memory - * -------------- <- 0x100000000 (4GB) - */ - res = upper_ram_end(dev, index++, - mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); - LOG_RESOURCE("high_ram", dev, res); + /* Add high RAM */ + const struct SystemMemoryMapHob *mm = get_system_memory_map(); + for (int i = 0; i < mm->numberEntries; i++) { + const struct SystemMemoryMapElement *e = &mm->Element[i]; + uint64_t addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); + if (addr < 4ULL * GiB) + continue; + if (!is_memtype_processor_attached(e->Type)) + continue; + if (is_memtype_reserved(e->Type)) + continue; + + res = ram_range(dev, index++, addr, size); + LOG_RESOURCE("high_ram", dev, res); + } + + if (CONFIG(SOC_INTEL_HAS_CXL)) { /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { @@ -320,10 +324,6 @@ else LOG_RESOURCE("CXL_memory", dev, res); } - } else { - /* 4GiB -> TOHM */ - res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1); - LOG_RESOURCE("high_ram", dev, res); } /* add MMIO CFG resource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Gerrit-Change-Number: 84304 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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