coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84629?usp=email ) Change subject: mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387 Gerrit-Change-Number: 84629 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:29:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/*: Don't disable Turbo Boost in Power Saver profile
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84628?usp=email ) Change subject: mb/starlabs/*: Don't disable Turbo Boost in Power Saver profile ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a Gerrit-Change-Number: 84628 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:28:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Hook up PCIe Power Management to option API
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81906?usp=email ) Change subject: soc/intel/alderlake: Hook up PCIe Power Management to option API ...................................................................... Patch Set 10: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81906/comment/f7eb1ddf_6c65946f?us… : PS8, Line 7: PCI > nit: PCIe Done https://review.coreboot.org/c/coreboot/+/81906/comment/d1b9c72a_c0d753c9?us… : PS8, Line 9: PCICLK_PM > Can't find this symbol Done File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81906/comment/bff174c6_658aa077?us… : PS8, Line 496: pciexp_aspm > It seems redundant execution of `get_uint_option()`. […] Done https://review.coreboot.org/c/coreboot/+/81906/comment/97a3072c_a2468cc2?us… : PS8, Line 535: bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); : bool pciexp_aspm = get_uint_option("pciexp_aspm", CONFIG(PCIEXP_ASPM)); : bool pciexp_l1_sub_state = get_uint_option("pciexp_l1_sub_state", : CONFIG(PCIEXP_L1_SUB_STATE)); > Sure Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Gerrit-Change-Number: 81906 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:22:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Hook up PCIe Power Management to option API
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81906?usp=email to look at the new patch set (#10). Change subject: soc/intel/alderlake: Hook up PCIe Power Management to option API ...................................................................... soc/intel/alderlake: Hook up PCIe Power Management to option API Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the option API. Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81906/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Gerrit-Change-Number: 81906 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XL] Change in coreboot[main]: mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant
by Matt DeVillier (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/74445?usp=email ) Change subject: mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737 Gerrit-Change-Number: 74445 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:20:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/starbook/tgl: Add USB ACPI to devicetree
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84271?usp=email ) Change subject: mb/starlabs/starbook/tgl: Add USB ACPI to devicetree ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84271/comment/5c4c7eb8_83cdc14f?us… : PS1, Line 8: > Please elaborate, and document how you tested this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I803a23007f49ea45abc68421e867535081e31b3f Gerrit-Change-Number: 84271 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:17:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/starlabs/starbook/tgl: Add USB ACPI to devicetree
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Sean Rhodes. Hello Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84271?usp=email to look at the new patch set (#2). Change subject: mb/starlabs/starbook/tgl: Add USB ACPI to devicetree ...................................................................... mb/starlabs/starbook/tgl: Add USB ACPI to devicetree Tested on Ubuntu 24.04 by verifying dmesg output and that USB 2.0 and 3.0 devices are registered correctly. Change-Id: I803a23007f49ea45abc68421e867535081e31b3f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84271/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I803a23007f49ea45abc68421e867535081e31b3f Gerrit-Change-Number: 84271 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Remove PMC GPIO routing
by Sean Rhodes (Code Review) 02 Oct '24

02 Oct '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84269?usp=email to look at the new patch set (#2). Change subject: mb/starlabs/starbook/tgl: Remove PMC GPIO routing ...................................................................... mb/starlabs/starbook/tgl: Remove PMC GPIO routing These aren't used so remove them. Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/84269/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb Gerrit-Change-Number: 84269 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: arch/x86: Shadow ROM tables into EBDA
by Felix Held (Code Review) 02 Oct '24

02 Oct '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84322?usp=email ) Change subject: arch/x86: Shadow ROM tables into EBDA ...................................................................... arch/x86: Shadow ROM tables into EBDA For platforms without writable PAM-F segment support (e.g. some simics virtual platforms), put ROM table pointers (e.g. ACPI/SMBIOS low pointers) into EBDA. Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Change-Id: I2aac74708279813f9a848044d470fdc980ea4305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84322 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/arch/x86/Kconfig M src/arch/x86/tables.c 2 files changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4737e3c..2db526e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -439,4 +439,11 @@ default 0x400 help The default value of EBDA size is 0x400. + +config SHADOW_ROM_TABLE_TO_EBDA + bool + default n + help + For platforms without writable PAM-F segment support. Put ROM table + pointers (e.g. ACPI/SMBIOS low pointers) into EBDA. endif diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 2732638..e47f1bc 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -192,7 +192,12 @@ void arch_write_tables(uintptr_t coreboot_table) { size_t sz; - unsigned long rom_table_end = 0xf0000; + unsigned long rom_table_end; + + if (CONFIG(SHADOW_ROM_TABLE_TO_EBDA)) + rom_table_end = CONFIG_DEFAULT_EBDA_SEGMENT << 4; + else + rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ if (CONFIG(GENERATE_PIRQ_TABLE)) @@ -224,4 +229,8 @@ const uintptr_t base = 0; bootmem_add_range(base, forwarding_table - base, BM_MEM_TABLE); + + /* Reserve Extend BIOS Data Area (EBDA) region explicitly */ + bootmem_add_range((uintptr_t)CONFIG_DEFAULT_EBDA_SEGMENT << 4, + CONFIG_DEFAULT_EBDA_SIZE, BM_MEM_TABLE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2aac74708279813f9a848044d470fdc980ea4305 Gerrit-Change-Number: 84322 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: soc/amd/glinda/.../iomap.h: Update for glinda
by Maximilian Brune (Code Review) 02 Oct '24

02 Oct '24

Attention is currently required from: Felix Held, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email ) Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84380/comment/89bc03ce_92403950?us… : PS4, Line 10: DMA4 apparently doesn't exist anymore so remove it. > no; it's just not visible in the ppr version you have access to :( I see. Thanks for checking. I updated the patch to only include the removal of the TODO now. File src/soc/amd/glinda/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84380/comment/80ef75d0_169cf3f1?us… : PS4, Line 35: #define APU_DMAC4_BASE 0xfedd0000 > this is still there; just not visible in the non-internal ppr. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Gerrit-Change-Number: 84380 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Oct 2024 14:15:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit October 2024