coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0
by Paul Menzel (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84909?usp=email ) Change subject: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84909/comment/dec79937_251af536?us… : PS1, Line 16: ``` : [WARN ] Unknown min d_state for PCI: 00:1f.4 : ``` As \`\`\` is not official Markdown, I’d use, especially for single lines, four spaces to mark code lines up. -- To view, visit https://review.coreboot.org/c/coreboot/+/84909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Gerrit-Change-Number: 84909 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 10:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add ACPI names for missing devices
by Paul Menzel (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84910?usp=email ) Change subject: soc/intel/pantherlake: Add ACPI names for missing devices ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84910/comment/3b3cf44e_8c54a80f?us… : PS1, Line 26: Signed-off-by: Subrata Banik <subratabanik(a)google.com> Move one line below? -- To view, visit https://review.coreboot.org/c/coreboot/+/84910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Gerrit-Change-Number: 84910 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 10:49:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add ACPI names for missing devices
by Subrata Banik (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84910?usp=email ) Change subject: soc/intel/pantherlake: Add ACPI names for missing devices ...................................................................... soc/intel/pantherlake: Add ACPI names for missing devices This patch adds ACPI names for the following devices: - THC0 (PCI: 00:10.0) - THC1 (PCI: 00:10.1) - SRAM (PCI: 00:14.2) - FSPI (PCI: 00:1f.5) TEST=Able to build and boot google/fatcat without any error. w/o this patch: ``` [ERROR] Missing ACPI Name for PCI: 00:10.0 [ERROR] Missing ACPI Name for PCI: 00:10.1 [ERROR] Missing ACPI Name for PCI: 00:14.2 [ERROR] Missing ACPI Name for PCI: 00:1f.5 ``` Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 --- M src/soc/intel/pantherlake/chip.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/84910/1 diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 2d9f67a..2202878 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -80,10 +80,13 @@ case PCI_DEVFN_TBT1: return "TRP1"; case PCI_DEVFN_TBT2: return "TRP2"; case PCI_DEVFN_TBT3: return "TRP3"; + case PCI_DEVFN_THC0: return "THC0"; + case PCI_DEVFN_THC1: return "THC1"; case PCI_DEVFN_NPU: return "NPU"; case PCI_DEVFN_IPU: return "IPU"; case PCI_DEVFN_ISH: return "ISHB"; case PCI_DEVFN_XHCI: return "XHCI"; + case PCI_DEVFN_SRAM: return "SRAM"; case PCI_DEVFN_I2C0: return "I2C0"; case PCI_DEVFN_I2C1: return "I2C1"; case PCI_DEVFN_I2C2: return "I2C2"; @@ -111,6 +114,7 @@ case PCI_DEVFN_GSPI1: return "SPI1"; /* Keeping ACPI device name coherent with ec.asl */ case PCI_DEVFN_ESPI: return "LPCB"; + case PCI_DEVFN_SPI: return "FSPI"; case PCI_DEVFN_HDA: return "HDAS"; case PCI_DEVFN_SMBUS: return "SBUS"; case PCI_DEVFN_GBE: return "GLAN"; -- To view, visit https://review.coreboot.org/c/coreboot/+/84910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Gerrit-Change-Number: 84910 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0
by Subrata Banik (Code Review) 29 Oct '24

29 Oct '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84909?usp=email ) Change subject: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0 ...................................................................... soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0 This change sets the SMBUS device to min sleep state D0 in the ACPI sleep state table. TEST=Able to build and boot google/fatcat. w/o this patch: ``` [WARN ] Unknown min d_state for PCI: 00:1f.4 ``` w/ this patch: No Error or Warning. Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84909/1 diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index fd17ef5..c49555b 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -225,6 +225,7 @@ { PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Gerrit-Change-Number: 84909 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Angel Pons (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Alexander Couzens, Cleyton Silva, Keith Hui. Angel Pons has posted comments on this change by Cleyton Silva. ( https://review.coreboot.org/c/coreboot/+/83670?usp=email ) Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... Patch Set 5: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83670/comment/90f0bccf_f24e9b16?us… : PS1, Line 13: 2MB+4MB > ./util/ifdtool -f rom.layout bkp-lenovo-h61.rom […] This doesn't show the flash chip order, though. Can you please show the output of `./util/ifdtool -d rom.layout bkp-lenovo-h61.rom`? https://review.coreboot.org/c/coreboot/+/83670/comment/295f9197_c6df43c0?us… : PS1, Line 43: - Internal flashing : - External flashing (in-circuit) > Yes, vendor firmware restricts internal flashing! […] Nice! Isn't it convenient that UEFI code reuse leads to exploit reuse? 😄 The main reason why there's a flashing instructions page for the ThinkPads is because there's several models that can use this approach. For your board, I believe you can document the flashing process in your mainboard's doc page (which you'd need to create), maybe linking to the Lenovo instructions if they're similar enough (mention what needs to be done differently on your mainboard page). If the ThinkPad instructions are generic enough, maybe they could be moved to a mainboard-agnostic place (where the flashing firmware instructions are). But it would be best to handle documentation changes in a separate commit. File src/mainboard/lenovo/ih61m/Kconfig: https://review.coreboot.org/c/coreboot/+/83670/comment/cb42d950_3ede97da?us… : PS4, Line 23: config MAINBOARD_PART_NUMBER : default "IH61M Ver:1.0" if BOARD_LENOVO_IH61M_V1 : default "IH61M Ver:4.2" if BOARD_LENOVO_IH61M_V4 Would it make more sense to set `MAINBOARD_VERSION` instead? ```suggestion config MAINBOARD_PART_NUMBER default "IH61M" config MAINBOARD_VERSION default "Ver:1.0" if BOARD_LENOVO_IH61M_V1 default "Ver:4.2" if BOARD_LENOVO_IH61M_V4 ``` File src/mainboard/lenovo/ih61m/early_init.c: https://review.coreboot.org/c/coreboot/+/83670/comment/11fecf2a_2e901de7?us… : PS4, Line 27: pnp_set_logical_device(SERIAL_DEV); This shouldn't be needed, `nuvoton_enable_serial` already switches to `SERIAL_DEV` -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 5 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 29 Oct 2024 09:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Cleyton Silva <pokecleyton(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Cleyton Silva (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Alexander Couzens, Angel Pons, Keith Hui. Hello Alexander Couzens, Angel Pons, Keith Hui, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83670?usp=email to look at the new patch set (#5). Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... mb/lenovo: Add IH61M mainboard This is based on the autoport output with some manual corrections. This mainboard is used in several Lenovo desktop models. It comes in two versions, Ver:1.0 and Ver:4.2. Version 1.0 has only a 4MB SPI chip and 4.2 has a 2MB+4MB array. The VBT was obtained with "intelvbttool -l -v data.vbt" from the vendor firmware version "F1KT54AUS". Works: - Ivy/Sandy Bridge CPUs - All USB ports - USB EHCI debug - All SATA ports - VGA - Ethernet - Audio - PCIe x16 slot - PCIe x1 slots - S3 suspend/resume - Libgfxinit - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - Internal flashing[1] Not Tested: - DVI-D - PS/2 - COM1/COM2 - LPT header - LPC_DEBUG header Does not work(?): - External flashing (in-circuit) [1]https://doc.coreboot.org/mainboard/lenovo/ivb_internal_flashing.html Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Signed-off-by: Cleyton Silva <pokecleyton(a)gmail.com> --- A src/mainboard/lenovo/ih61m/Kconfig A src/mainboard/lenovo/ih61m/Kconfig.name A src/mainboard/lenovo/ih61m/Makefile.mk A src/mainboard/lenovo/ih61m/acpi/ec.asl A src/mainboard/lenovo/ih61m/acpi/platform.asl A src/mainboard/lenovo/ih61m/acpi/superio.asl A src/mainboard/lenovo/ih61m/board_info.txt A src/mainboard/lenovo/ih61m/cmos.default A src/mainboard/lenovo/ih61m/cmos.layout A src/mainboard/lenovo/ih61m/data.vbt A src/mainboard/lenovo/ih61m/devicetree.cb A src/mainboard/lenovo/ih61m/dsdt.asl A src/mainboard/lenovo/ih61m/early_init.c A src/mainboard/lenovo/ih61m/gma-mainboard.ads A src/mainboard/lenovo/ih61m/gpio.c A src/mainboard/lenovo/ih61m/hda_verb.c A src/mainboard/lenovo/ih61m/mainboard.c 17 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83670/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 5 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Cleyton Silva (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Alexander Couzens, Angel Pons, Keith Hui. Cleyton Silva has posted comments on this change by Cleyton Silva. ( https://review.coreboot.org/c/coreboot/+/83670?usp=email ) Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83670/comment/7459716a_6c617aa8?us… : PS1, Line 13: 2MB+4MB > Huh, interesting. ./util/ifdtool -f rom.layout bkp-lenovo-h61.rom cat rom.layout 00000000:00000fff fd 00200000:005fffff bios 00001000:001fffff me 00fff000:00000fff gbe 00fff000:00000fff pd (the gbe and pd regions do not exist in the vendor firmware, so in order to use the rom.layout with the flashrom I had to delete the last two lines) https://review.coreboot.org/c/coreboot/+/83670/comment/d1923261_a0d02fe5?us… : PS1, Line 43: - Internal flashing : - External flashing (in-circuit) > You might be able to flash internally with `--ifd -i bios`. […] Yes, vendor firmware restricts internal flashing! The flashrom outputs below are only from Version:4.2. Both versions have a “ME_DIS” jumper and when it is in position “1” it is possible to read the chips completely, but it is not possible to write in any region. In its original position “0” it is only possible to read the fd and bios regions, and it is also not possible to write in any region. When trying to flash coreboot the flashrom outputs are… -JUMPER ME_DIS=0 > https://pastebin.com/raw/4kARcANE -JUMPER ME_DIS=1 > https://pastebin.com/raw/iPT41tjB The board has a “SPI_DEBUG1” header for external flashing. I connected the wires but I couldn’t communicate with the chips. I don’t know if I made a mistake… BUT GOOD NEWS! After a few days of free time, I managed to flash the internal flash using CHIPSEC (uefi s3bootscript) following this tutorial: https://doc.coreboot.org/mainboard/lenovo/ivb_internal_flashing.html I will update the commit message to this fact. I haven’t checked yet if it’s still possible to do this using the latest firmware version from the vendor. Flashrom output of successful flashing (bios region only): https://pastebin.com/raw/QfyGTCui Will it be necessary to make a specific flash tutorial for this motherboard? -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 4 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 29 Oct 2024 09:19:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Cleyton Silva <pokecleyton(a)gmail.com>

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Cleyton Silva (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Alexander Couzens, Cleyton Silva, Keith Hui. Hello Alexander Couzens, Angel Pons, Keith Hui, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83670?usp=email to look at the new patch set (#4). Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... mb/lenovo: Add IH61M mainboard This is based on the autoport output with some manual corrections. This mainboard is used in several Lenovo desktop models. It comes in two versions, Ver:1.0 and Ver:4.2. Version 1.0 has only a 4MB SPI chip and 4.2 has a 2MB+4MB array. The VBT was obtained with "intelvbttool -l -v data.vbt" from the vendor firmware version "F1KT54AUS". Works: - Ivy/Sandy Bridge CPUs - All USB ports - USB EHCI debug - All SATA ports - VGA - Ethernet - Audio - PCIe x16 slot - PCIe x1 slots - S3 suspend/resume - Libgfxinit - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - DVI-D - PS/2 - COM1/COM2 - LPT header - LPC_DEBUG header - Internal flashing[1] Does not work(?): - External flashing (in-circuit) [1]https://doc.coreboot.org/mainboard/lenovo/ivb_internal_flashing.html Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Signed-off-by: Cleyton Silva <pokecleyton(a)gmail.com> --- A src/mainboard/lenovo/ih61m/Kconfig A src/mainboard/lenovo/ih61m/Kconfig.name A src/mainboard/lenovo/ih61m/Makefile.mk A src/mainboard/lenovo/ih61m/acpi/ec.asl A src/mainboard/lenovo/ih61m/acpi/platform.asl A src/mainboard/lenovo/ih61m/acpi/superio.asl A src/mainboard/lenovo/ih61m/board_info.txt A src/mainboard/lenovo/ih61m/cmos.default A src/mainboard/lenovo/ih61m/cmos.layout A src/mainboard/lenovo/ih61m/data.vbt A src/mainboard/lenovo/ih61m/devicetree.cb A src/mainboard/lenovo/ih61m/dsdt.asl A src/mainboard/lenovo/ih61m/early_init.c A src/mainboard/lenovo/ih61m/gma-mainboard.ads A src/mainboard/lenovo/ih61m/gpio.c A src/mainboard/lenovo/ih61m/hda_verb.c A src/mainboard/lenovo/ih61m/mainboard.c 17 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83670/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 4 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: mb/google/nissa/var/teliks: Match VBT with SSFC
by Eric Lai (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Qinghong Zeng, Weimin Wu. Eric Lai has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/84871?usp=email ) Change subject: mb/google/nissa/var/teliks: Match VBT with SSFC ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee Gerrit-Change-Number: 84871 Gerrit-PatchSet: 15 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Edward Dai <edwarddai(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ricky Chang <rickytlchang(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 09:05:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/teliks: Match VBT with SSFC
by Subrata Banik (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Qinghong Zeng, Weimin Wu. Subrata Banik has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/84871?usp=email ) Change subject: mb/google/nissa/var/teliks: Match VBT with SSFC ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee Gerrit-Change-Number: 84871 Gerrit-PatchSet: 15 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Edward Dai <edwarddai(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ricky Chang <rickytlchang(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 09:04:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit October 2024