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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
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Change subject: mb/google/dedede/var/awasuki: Decrease touchpad I2C freq below 400 kHz
......................................................................
mb/google/dedede/var/awasuki: Decrease touchpad I2C freq below 400 kHz
Modify the I2C frequency of the touchpad between 380 Khz and 400 Khz
to meet the spec.
Before:
I2C0 - 420KHz
After:
I2C0 - 398Khz
BUG=b:351968527
TEST=Check that the wave form meets the spec.
Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d
Signed-off-by: Wei Hualin <weihualin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84898/5
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Change subject: mb/lenovo: Add IH61M mainboard
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83670/comment/049455f8_d55c39b9?us… :
PS1, Line 13: 2MB+4MB
> I don't know why ifdtool is showing the regions out of order, besides gbe and pd which aren't even u […]
Regions in ifdtool's output are ordered by index.
```
Component 2 Density: 4MB
Component 1 Density: 2MB
```
Okay, interesting. So it's 2+4.
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Change subject: mb/lenovo: Add IH61M mainboard
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83670/comment/071d9d27_58ba17d4?us… :
PS1, Line 13: 2MB+4MB
> This doesn't show the flash chip order, though. Can you please show the output of `. […]
I don't know why ifdtool is showing the regions out of order, besides gbe and pd which aren't even used on this board, but the hex addresses where each region starts/ends are correct, organized like this...
00000000:00000fff fd
00001000:001fffff me
00200000:005fffff bios
./util/ifdtool -d bkp-lenovo-h61.rom > https://pastebin.com/raw/Yx7jbv7rhttps://review.coreboot.org/c/coreboot/+/83670/comment/6c2f023c_9004963f?us… :
PS1, Line 43: - Internal flashing
: - External flashing (in-circuit)
> Nice! Isn't it convenient that UEFI code reuse leads to exploit reuse? 😄 […]
Very convenient! =)
Okay, I'll make another separate commit later to document the flashing for this board. Thanks, Angel!
File src/mainboard/lenovo/ih61m/Kconfig:
https://review.coreboot.org/c/coreboot/+/83670/comment/980a10f3_8a4f633e?us… :
PS4, Line 23: config MAINBOARD_PART_NUMBER
: default "IH61M Ver:1.0" if BOARD_LENOVO_IH61M_V1
: default "IH61M Ver:4.2" if BOARD_LENOVO_IH61M_V4
> Would it make more sense to set `MAINBOARD_VERSION` instead? […]
Acknowledged
File src/mainboard/lenovo/ih61m/early_init.c:
https://review.coreboot.org/c/coreboot/+/83670/comment/77bf4eb6_639144ad?us… :
PS4, Line 27: pnp_set_logical_device(SERIAL_DEV);
> This shouldn't be needed, `nuvoton_enable_serial` already switches to `SERIAL_DEV`
Acknowledged
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Change subject: soc/intel/pantherlake: Add ACPI names for missing devices
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/pantherlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/84903/comment/d020b24b_1a20abb9?us… :
PS1, Line 28: static void save_dimm_info(void)
This looks very similar to other Intel SOC implementations. Isn’t this only dependent on the FSP version, and could be unified?
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Change subject: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0
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Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/riven: Configure Acoustic noise mitigation
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84908/comment/256ad999_75806a94?us… :
PS3, Line 8:
Maybe add:
> Follow the thermal team’s recommendation:
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