coreboot-gerrit October 2024

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[XS] Change in coreboot[main]: [only for test] lz4/lib; Build test using C23
by Julius Werner (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Elyes Haouas. Julius Werner has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84892?usp=email ) Change subject: [only for test] lz4/lib; Build test using C23 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Do not change this library. We want to keep it in sync with upstream as much as possible. -- To view, visit https://review.coreboot.org/c/coreboot/+/84892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dae74eca85b41d15ebfd4015631bb7efc5dbf75 Gerrit-Change-Number: 84892 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 29 Oct 2024 20:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: commonlib/device_tree: Use boolean instead of int
by Julius Werner (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Elyes Haouas. Julius Werner has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84911?usp=email ) Change subject: commonlib/device_tree: Use boolean instead of int ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: Didn't we have this discussion before? https://doc.coreboot.org/contributing/coding_style.html#function-return-val… -- To view, visit https://review.coreboot.org/c/coreboot/+/84911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf938c24d067c9d15faf45b6072e150f0aedfe08 Gerrit-Change-Number: 84911 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 29 Oct 2024 20:32:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Adjust EC host command range for Fatcat
by Subrata Banik (Code Review) 29 Oct '24

29 Oct '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84919?usp=email ) Change subject: mb/google/fatcat: Adjust EC host command range for Fatcat ...................................................................... mb/google/fatcat: Adjust EC host command range for Fatcat This commit adjusts the EC host command range for the Fatcat board to 0x800-0x807 & 0x200-0x20f. This change is necessary because the microchip EC used on the Fatcat board has a smaller host command range than the ITE/Nuvoton ECs used on other Fatcat variants. The `gen1_dec` register in the devicetree is updated to reflect this change. As per boot log, the `gen1_dec` aka offset 0x84, base address is 800 and size is 8 bytes. AP FW Boot log: [SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84 BUG=b:376207365 TEST=Able to build and boot google/fatcat w/o any error. without this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 [ERROR] LPC: Cannot open IO window: 800 size 8 [ERROR] No more IO windows with this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84919/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index d794925..1b1fc73 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -4,8 +4,11 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" + # For Fatcat (with microchip EC): + # EC host command ranges are in 0x800-0x807 & 0x200-0x20f + # For other Fatcat variants (with ITE/Nuvoton EC): + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) ? 0x00040801 : 0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" -- To view, visit https://review.coreboot.org/c/coreboot/+/84919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Gerrit-Change-Number: 84919 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time
by Bora Guvendik (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Elyes Haouas, Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/fatcat/Kconfig: https://review.coreboot.org/c/coreboot/+/84872/comment/1970132f_0531be05?us… : PS6, Line 34: SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY > isn't this already selected through […] With this change, I am not selecting cse_telemetry_v1.h or cse_telemetry_v2.h for PTL (since v1 or v2 doesn't match PTL definitions). So PERF_DATA_CSME_GET_PERF_RESPONSE is not defined. File src/soc/intel/pantherlake/cse_telemetry.c: https://review.coreboot.org/c/coreboot/+/84872/comment/3260846a_e74f87ee?us… : PS6, Line 9: #define PERF_DATA_CSME_GET_PERF_RESPONSE 63 > I'm confused. […] no its not, explained in previous comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 29 Oct 2024 18:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration
by Cliff Huang (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email ) Change subject: soc/intel/common/gpio: add function to lock GPIO configuration ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabe4e4b1d282a5f6cae8f330100c9139e0c2691d Gerrit-Change-Number: 84901 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 18:08:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time
by Elyes Haouas (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Bora Guvendik, Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. Elyes Haouas has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/fatcat/Kconfig: https://review.coreboot.org/c/coreboot/+/84872/comment/2fc2c810_91686a3d?us… : PS6, Line 34: SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY isn't this already selected through `config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 bool select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY help This config will make mainboard use version 1 of the CSE timestamp definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 bool select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY help This config will make mainboard use version 2 of the CSE timestamp definitions, it can be used for Meteor Lake M/P. ` ? File src/soc/intel/pantherlake/cse_telemetry.c: https://review.coreboot.org/c/coreboot/+/84872/comment/fec392b7_fb8f5856?us… : PS6, Line 9: #define PERF_DATA_CSME_GET_PERF_RESPONSE 63 I'm confused. This already defined as 63, isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 18:07:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time
by Bora Guvendik (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/84872?usp=email ) Change subject: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > sorry unable to follow the reason behind removing the provision to capture pre-cpu reset boot time i […] I created a partner bug for this b:376218080 -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 17:56:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time
by Bora Guvendik (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Bora Guvendik, Kapil Porwal, Pranava Y N, Wonkyu Kim. Hello Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84872?usp=email to look at the new patch set (#6). Change subject: soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time ...................................................................... soc/intel/pantherlake: Simplify Panther Lake's pre-cpu time Before this change, the timestamp data displayed was not accurate since Panther Lake uses new definitions. Instead of updating new definitions gen over gen, change it to display only total pre-CPU time in firmware. Detailed pre-cpu time can be extracted via OS tool. 990:CSME ROM started execution 0 0:1st timestamp 698,762 BUG=b:376218080 TEST=fatcat no longer shows inaccurate pre-cpu telemetry data Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee --- M src/mainboard/google/fatcat/Kconfig M src/soc/intel/pantherlake/cse_telemetry.c 2 files changed, 2 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/84872/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Gerrit-Change-Number: 84872 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: soc/amd/common/acpi: Add SPI flash controller
by Ana Carolina Cabral (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84918?usp=email ) Change subject: soc/amd/common/acpi: Add SPI flash controller ...................................................................... soc/amd/common/acpi: Add SPI flash controller Add the ACPI code for the flash SPI controller. Change-Id: I0f2c1e3351671ad47fbe5c890e4f99d2e19dbfbf Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- A src/soc/amd/common/acpi/spi.asl 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84918/1 diff --git a/src/soc/amd/common/acpi/spi.asl b/src/soc/amd/common/acpi/spi.asl new file mode 100644 index 0000000..6a5e0a3 --- /dev/null +++ b/src/soc/amd/common/acpi/spi.asl @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/spi_defs.h> + + Mutex (ASM1, 0) //Amd Spi1 Semaphore Mutex + Name (SVBF, Buffer (0x100) {0}) + CreateWordField(SVBF, 0x014, RG22) + CreateDWordField(SVBF, 0x018, SAR2) +#include <soc/iomap.h> + +Device(SPI1) { // SPI controller + Name(_HID, "AMDI0062") + Name(_UID, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } // end of Method _STA + OperationRegion(SPIM, SystemMemory, SPI_BASE_ADDRESS , 0x100) // SPI Mmio Register + Field(SPIM, AnyAcc, NoLock, Preserve) { + Offset (0x1D), + ASCE,2, // AltSpiCsEn + Offset (SPI100_SPEED_CONFIG), + SSSC, 16, // SPIx22 SPI100 Speed Config + Offset (SPI_MISC_CNTRL), + STRN,1, // Spi TuRN + , 2, + BOWS,1, //Bios OWnerShip + DOWS,1, //Driver OWnerShip + } + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed(ReadWrite, 0xFEC10000, 0x100) + }) // End of Name (RBUF + Return (RBUF) + } // End of Method _CRS + + Method(ASSC, 2, Serialized) //Amd Spi Semaphore Control Arg0:Request ID Arg1:Timeout in Micro Second + { + Acquire (ASM1, 0xFFFF) + Store (Arg1, Local0) //save timeout + Switch (ToInteger(Arg0)) + { + Case (3) //Driver Acquire Spi Bus + { + store (one, DOWS) + store (one, STRN) + while (LAnd(BOWS,STRN)) { + if (Arg1) { + stall (1) + Subtract (Local0, one, Local0) + if (LEqual(Local0, zero)) { Break } + } + } + //store (RAR2, SAR2) //TODO SPI_ENTRY + //store (zero,RAR2) //TODO SPI_ENTRY + store (2, ASCE) + store (SSSC, RG22) + } + Case (4) //Driver Release Spi Bus + { + store (RG22, SSSC) + store (zero, ASCE) + //store (SAR2, RAR2)//TODO SPI_ENTRY + store (one, Local0) + store (zero, DOWS) + } + } + Release (ASM1) + Return (Local0) + } + } // End Device SPI1 \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/84918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f2c1e3351671ad47fbe5c890e4f99d2e19dbfbf Gerrit-Change-Number: 84918 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/common/spi: Create header for SPI defines
by Ana Carolina Cabral (Code Review) 29 Oct '24

29 Oct '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84917?usp=email ) Change subject: soc/amd/common/spi: Create header for SPI defines ...................................................................... soc/amd/common/spi: Create header for SPI defines Move SPI defines to header file so they can be used in asl files. Change-Id: I24de8c05a65c915bd4979d91bd1c2bfa6864b752 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/spi.h A src/soc/amd/common/block/include/amdblocks/spi_defs.h 2 files changed, 64 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84917/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eafc2c2..535b261 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -6,8 +6,7 @@ #include <thread.h> #include <types.h> -#define SPI_CNTRL0 0x00 -#define SPI_BUSY BIT(31) +#include "spi_defs.h" enum spi_read_mode { SPI_READ_MODE_NORMAL33M = 0, @@ -19,28 +18,7 @@ SPI_READ_MODE_NORMAL66M = 6, SPI_READ_MODE_FAST_READ = 7, }; -/* - * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for - * SpiReadMode. - */ -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) -#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) -#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ - SPI_READ_MODE_LOWER_BITS(x)) -#define SPI_ACCESS_MAC_ROM_EN BIT(22) -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) -#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) -#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) -#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ - DECODE_SPI_MODE_LOWER_BITS(x)) - -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI100_SPEED_CONFIG 0x22 enum spi100_speed { SPI_SPEED_66M = 0, SPI_SPEED_33M = 1, @@ -50,37 +28,6 @@ SPI_SPEED_800K = 5, }; -#define SPI_SPEED_MASK 0xf -#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) -#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) -#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) -#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) -#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) - -#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ - SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) - -#define DECODE_SPEED_MASK 0x07 -#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) -#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) -#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) -#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) -#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - -#define SPI_ROM_PAGE 0x5c - -#define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) - -#define SPI_MISC_CNTRL 0xfc -/* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize - access to the SPI controller between SMM and non-SMM software/OS driver. */ -#define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4) - struct spi_config { /* * Default values if not overridden by mainboard: diff --git a/src/soc/amd/common/block/include/amdblocks/spi_defs.h b/src/soc/amd/common/block/include/amdblocks/spi_defs.h new file mode 100644 index 0000000..b9a06e3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi_defs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_SPI_DEFS_H +#define AMD_BLOCK_SPI_DEFS_H + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) +#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) +#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) +#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ + DECODE_SPI_MODE_LOWER_BITS(x)) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define DECODE_SPEED_MASK 0x07 +#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) +#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) +#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) +#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) +#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_ROM_PAGE 0x5c + +#define SPI_FIFO 0x80 +#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) + +#define SPI_MISC_CNTRL 0xfc +/* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize + access to the SPI controller between SMM and non-SMM software/OS driver. */ +#define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4) + + +#endif /* AMD_BLOCK_DATA_FABRIC_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24de8c05a65c915bd4979d91bd1c2bfa6864b752 Gerrit-Change-Number: 84917 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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coreboot-gerrit October 2024