coreboot-gerrit September 2023

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[XS] Change in coreboot[master]: drivers/aspeed/common/ast_drv.h: Use C99 flexible arrays
by Maximilian Brune (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Elyes Haouas, Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76844?usp=email ) Change subject: drivers/aspeed/common/ast_drv.h: Use C99 flexible arrays ...................................................................... Patch Set 2: (1 comment) File src/drivers/aspeed/common/ast_drv.h: https://review.coreboot.org/c/coreboot/+/76844/comment/ef8b12ba_025efdc7 : PS2, Line 251: struct drm_format { : u32 cpp[]; /* Colors per pixel */ : }; : > Unfortunately, this gives an error. […] Can't we just replace ``` u32 cpp[1]; ``` with ``` u32 cpp; ``` ? Looking at the references of the "cpp" property in the coreboot tree it seems like only the first element is always referenced and its not actually used in a flexible array manner. -- To view, visit https://review.coreboot.org/c/coreboot/+/76844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489347532e00581accaabad9ea4a3e0ad22f78f2 Gerrit-Change-Number: 76844 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 02 Sep 2023 00:04:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient...
by Jérémy Compostella (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Arthur Heymans, Sridhar Siricilla. Hello Arthur Heymans, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77615?usp=email to look at the new patch set (#3). Change subject: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores ...................................................................... [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores commit b793aa3bca5a3f8a6c4ef5a28925a1aeebf426c8 ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm leads to the creation of invalid `Local x2APIC' entries in the MADT (APIC) ACPI table. It results in the kernel either: 1. Filtering them out when the random ID >= MAX_LOCAL_APIC (32768) 2. Fail to filter out when because the ID ends up being a negative number (0xfxxxxxxx) leading to efficient core(s) being considered bad and disabled. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/arch/x86/cpu.c M src/soc/intel/common/block/acpi/cpu_hybrid.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/77615/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/77615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Gerrit-Change-Number: 77615 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient...
by Jérémy Compostella (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Arthur Heymans, Sridhar Siricilla. Hello Arthur Heymans, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77615?usp=email to look at the new patch set (#2). Change subject: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores ...................................................................... [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores commit b793aa3bca5a3f8a6c4ef5a28925a1aeebf426c8 ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm leads to the creation of invalid `Local x2APIC' entries in the MADT (APIC) ACPI table. It results in the kernel either: 1. Filtering them out when the random ID >= MAX_LOCAL_APIC (32768) 2. Fail to filter out when because the ID ends up being a negative number (0xfxxxxxxx) leading to efficient core(s) being considered bad and disabled. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/77615/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Gerrit-Change-Number: 77615 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient...
by Jérémy Compostella (Code Review) 02 Sep '23

02 Sep '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77615?usp=email ) Change subject: [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores ...................................................................... [UNDERTESTS] soc/intel/common: Fix creation of non-existant efficient cores commit b793aa3bca5a3f8a6c4ef5a28925a1aeebf426c8 ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm leads to the creation of invalid `Local x2APIC' entries in the MADT (APIC) ACPI table. It results in the kernel either: 1. Filtering them out when the random ID >= MAX_LOCAL_APIC (32768) 2. Fail to filter out when because the the ID ends up being a negative number (0xfxxxxxxx) leading to efficient core(s) being considered bad and disabled. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/77615/1 diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 9a7b768..a252be2 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -54,12 +54,19 @@ uint32_t i, j = 0; for (i = 0; i < ARRAY_SIZE(cpu_apic_info.apic_ids); i++) { - if (cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF) + switch (cpu_infos[i].cpu->path.apic.core_type) { + case CPU_TYPE_PERF: cpu_apic_info.apic_ids[perf_core_cnt++] = cpu_infos[i].cpu->path.apic.apic_id; - else + break; + + case CPU_TYPE_EFF: eff_apic_ids[eff_core_cnt++] = cpu_infos[i].cpu->path.apic.apic_id; + break; + default: + /* Skip */ + } } if (perf_core_cnt > 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/77615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Gerrit-Change-Number: 77615 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Add functions for getting address bits taken by MKTME
by Cliff Huang (Code Review) 02 Sep '23

02 Sep '23

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77614?usp=email ) Change subject: soc/intel/common: Add functions for getting address bits taken by MKTME ...................................................................... soc/intel/common: Add functions for getting address bits taken by MKTME get_tme_bit_size(): Get number of address bits used by TME get_reserved_address_bits(): Get number of address bits taken by enabled features. Add defines for TME_ACTIVATE MSR BUG=288978352 TEST=Boot to OS and check the address bits from ACPI DMAR table Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/77614/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c317e05..f0ad45b 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -501,6 +501,22 @@ wrmsr(MSR_CORE_MKTME_ACTIVATION, msr); } +int get_tme_bit_size(void) +{ + if (is_tme_supported()) { + msr_t msr = rdmsr(MSR_IA32_TME_ACTIVATE); + if (msr.lo & MSR_IA32_TME_ACTIVATE_HW_ENCRYPT_EN) + return (msr.hi >> (MSR_IA32_TME_ACTIVATE_MK_TME_KEYID_BITS_SHIFT - 32)) & + MSR_IA32_TME_ACTIVATE_MK_TME_KEYID_BITS_MASK; + } + return 0; +} + +uint32_t get_reserved_address_bits(void) +{ + return get_tme_bit_size(); +} + /* Provide the max turbo frequency of the CPU */ unsigned int smbios_cpu_get_max_speed_mhz(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index cbc9e44..756fd03 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -208,6 +208,21 @@ void set_tme_core_activate(void); /* + * Get number of address bits used by TME + * + * Returns TME_ACTIVATE[MK_TME_KEYID_BITS] ( MSR 0x982 Bits[32-35]) if TME is enaabled + * NOTE: This function should be called after MK-TME features has been configured in the MSRs + * according to the capabilities and platform configuration. For instance, after romstage FSP. + */ +int get_tme_bit_size(void); + +/* + * Returns number of bits occupied in the address bits + * + */ +uint32_t get_reserved_address_bits(void); + +/* * This function checks if the CPU supports SGX feature. * Returns true if SGX feature is supported otherwise false. */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 9f95e9f..e9d7651 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -96,6 +96,11 @@ #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) +#define MSR_IA32_TME_ACTIVATE 0x982 +#define MSR_IA32_TME_ACTIVATE_HW_ENCRYPT_EN (1 << 1) +#define MSR_IA32_TME_ACTIVATE_MK_TME_KEYID_BITS_SHIFT 32 +#define MSR_IA32_TME_ACTIVATE_MK_TME_KEYID_BITS_MASK (0xf) + #define MSR_CORE_MKTME_ACTIVATION 0x9ff /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 -- To view, visit https://review.coreboot.org/c/coreboot/+/77614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 Gerrit-Change-Number: 77614 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: [Please Test] payloads/libpayload/drivers/usb/ehci_private: Use C99 f...
by Maximilian Brune (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Elyes Haouas, Felix Held, Patrick Georgi. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76850?usp=email ) Change subject: [Please Test] payloads/libpayload/drivers/usb/ehci_private: Use C99 flexible arrays ...................................................................... Patch Set 3: (1 comment) File payloads/libpayload/drivers/usb/ehci_private.h: PS1: > without having really looked into the details, it seems to me that this packed struct is used to acc […] we could replace it with a union instead. Maybe like this: ``` u32 configflag; union { portsc_t portsc; u8 res2[0x40]; } __packed; u32 hostpc; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/76850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5bb3da8205326a43bba44630a8fcdcac651184 Gerrit-Change-Number: 76850 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 01 Sep 2023 23:10:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86: Fixes for getting actual physical address bits
by Cliff Huang (Code Review) 02 Sep '23

02 Sep '23

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77613?usp=email ) Change subject: arch/x86: Fixes for getting actual physical address bits ...................................................................... arch/x86: Fixes for getting actual physical address bits Add cpu_max_phys_address_size() to get the physical address bits without being taking by any new features. cpu_phys_address_size() is now returning the actual bits by considering reserved bits taken by enabled SOC/CPU features. BUG=288978352 TEST=NA; This can not be tested alone. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d --- M src/arch/x86/cpu_common.c M src/include/cpu/cpu.h 2 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/77613/1 diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index e674afa..9dcc951 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -3,6 +3,8 @@ #include <cpu/cpu.h> #include <types.h> +uint32_t get_reserved_address_bits(void); + #if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -44,13 +46,40 @@ return cpuid_eax(0x80000000); } +/* + * NOTE: cpu_phys_address_size() should be called after CPU features + * has been configured, where SOC capabilities are checked and + * features are enabled in the MSRs according to the platform. For + * instance, MK-TME. Use cpu_max_phys_address_size() to get + * the maximum address bit size. + */ +int cpu_max_phys_address_size(void) +{ + if (!(cpu_have_cpuid())) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) { + return (cpuid_eax(0x80000008) & 0xff); + } + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + return 32; +} + +/* + * This function is implemented in the SOC-specific cpu lib. + */ +uint32_t __weak get_reserved_address_bits(void) { return 0; } + int cpu_phys_address_size(void) { if (!(cpu_have_cpuid())) return 32; - if (cpu_cpuid_extended_level() >= 0x80000008) - return cpuid_eax(0x80000008) & 0xff; + if (cpu_cpuid_extended_level() >= 0x80000008) { + return (cpuid_eax(0x80000008) & 0xff) - get_reserved_address_bits(); + } if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) return 36; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index fc662ee..482f26e 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,6 +9,7 @@ void cpu_initialize(void); uintptr_t cpu_get_lapic_addr(void); struct bus; +int cpu_max_phys_address_size(void); int cpu_phys_address_size(void); #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/77613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Gerrit-Change-Number: 77613 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: commonlib/bsd/tpm_log_defs.h: Use C99 flexible arrays
by Maximilian Brune (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Martin L Roth, Sergii Dmytruk. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76787?usp=email ) Change subject: commonlib/bsd/tpm_log_defs.h: Use C99 flexible arrays ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Patchset: PS2: > I have nothing against dropping the field and modifying `cbmem` and would prefer this solution over […] If we want to be ISO 99 compliant we have to remove the event property at the end of the tcpa_log_entry_header struct, since it is included in the tcpa_spec_entry struct. Therefore I would prefer the "ugly" conversion in cbmem (like it is implemented in the latest patchset) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/76787/comment/3598eb82_ff4d6ea4 : PS5, Line 915: uint8_t *ptr = (uint8_t *)log_entry + sizeof(*log_entry); nit: maybe use something like "event_ptr" instead of "ptr". -- To view, visit https://review.coreboot.org/c/coreboot/+/76787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b08b81d5df7a7500faa2c88d04f13dde05b6ea8 Gerrit-Change-Number: 76787 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 01 Sep 2023 22:05:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: [test] [do not merge] Rex: Add debug prints for TME debug
by Anil Kumar K (Code Review) 02 Sep '23

02 Sep '23

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77612?usp=email ) Change subject: [test] [do not merge] Rex: Add debug prints for TME debug ...................................................................... [test] [do not merge] Rex: Add debug prints for TME debug Change-Id: I9128857ec381a3fa74fd11af721f08b8b43659b8 --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/77612/1 diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bb5b6e7..c7bf9d1 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -190,6 +190,12 @@ m_cfg->TmeExcludeBase = (ram_top - 16*MiB); m_cfg->TmeExcludeSize = 16*MiB; } + + printk(BIOS_DEBUG, "TmeEnable = %d\n", m_cfg->TmeEnable); + printk(BIOS_DEBUG, "Tme GenerateNewTmeKey = %d\n", m_cfg->GenerateNewTmeKey); + printk(BIOS_DEBUG, "TmeExcludeBase = 0x%llx\n", m_cfg->TmeExcludeBase); + printk(BIOS_DEBUG, "TmeExcludeSize = 0x%llx\n", m_cfg->TmeExcludeSize); + } static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/77612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9128857ec381a3fa74fd11af721f08b8b43659b8 Gerrit-Change-Number: 77612 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: docs: Build in parallel
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Nicholas Chin, Nico Huber. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77452?usp=email ) Change subject: docs: Build in parallel ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25996f17348505722f3489a15a975de620331b5a Gerrit-Change-Number: 77452 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:50:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2023