coreboot-gerrit September 2023

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: remove SD_ABSENT
by Martin L Roth (Code Review) 02 Sep '23

02 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77596?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/screebo: remove SD_ABSENT ...................................................................... mb/google/rex/var/screebo: remove SD_ABSENT Remove SD_ABSENT since it's not being used, and CBI FW_CONFIG in current build does not reflect this config neither. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Signed-off-by: YH Lin <yueherngl(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77596 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 63c753e..1774bc7 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -19,9 +19,8 @@ option TOUCHSCREEN_ELAN 2 end field DB_SD 11 12 - option SD_ABSENT 0 - option SD_GL9750 1 - option SD_RTS5227S 2 + option SD_GL9750 0 + option SD_RTS5227S 1 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/77596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Gerrit-Change-Number: 77596 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Enable Weida touchscreen
by Martin L Roth (Code Review) 02 Sep '23

02 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77575?usp=email ) Change subject: mb/google/nissa/var/uldren: Enable Weida touchscreen ...................................................................... mb/google/nissa/var/uldren: Enable Weida touchscreen Support Weida WDT8790A touchscreen. BUG=b:297453122 BRANCH=firmware-brya-14505.B TEST=touchscreen is workable and evtest shows WDHT2601 $evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: sof-cs42l42 HDMI/DP,pcm=2 /dev/input/event11: sof-cs42l42 HDMI/DP,pcm=3 /dev/input/event12: sof-cs42l42 HDMI/DP,pcm=4 /dev/input/event13: sof-cs42l42 HDMI/DP,pcm=5 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchpad /dev/input/event5: WDHT2601:00 2575:0921 /dev/input/event6: WDHT2601:00 2575:0921 Stylus /dev/input/event7: WDHT2601:00 2575:0921 Stylus /dev/input/event8: DELL Dell USB Entry Keyboard /dev/input/event9: sof-cs42l42 Headset Jack Change-Id: If9539afaf891c8352bc7fc8e548fd77ea57ea6ca Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77575 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved Ian Feng: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index 3b9ecab..6a7d357 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -16,6 +16,7 @@ option TOUCHSCREEN_EKTH5012 4 option TOUCHSCREEN_WDT8752A 5 option TOUCHSCREEN_GTCH7502 6 + option TOUCHSCREEN_WDT8790A 7 end field EXT_VR 14 14 option EXT_VR_PRESENT 0 @@ -300,6 +301,24 @@ probe TOUCHSCREEN TOUCHSCREEN_GTCH7502 end end + chip drivers/i2c/hid + register "generic.hid" = ""WDHT2601"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "130" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 3c on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + probe TOUCHSCREEN TOUCHSCREEN_WDT8790A + end + end end device ref i2c3 on chip drivers/i2c/cs42l42 -- To view, visit https://review.coreboot.org/c/coreboot/+/77575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9539afaf891c8352bc7fc8e548fd77ea57ea6ca Gerrit-Change-Number: 77575 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex/var/karis: Enable ELAN touchscreen
by Martin L Roth (Code Review) 02 Sep '23

02 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77592?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/karis: Enable ELAN touchscreen ...................................................................... mb/google/rex/var/karis: Enable ELAN touchscreen BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I179df1e0e544783f77a485ad08293530e8a86ecd Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77592 Reviewed-by: Eran Mitrani <mitrani(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/karis/overridetree.cb 1 file changed, 8 insertions(+), 7 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eran Mitrani: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 04e21ba..7bde6bc 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -378,20 +378,21 @@ end #I2C0 device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN6918"" + register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" - register "generic.enable_delay_ms" = "1" + register "generic.enable_delay_ms" = "6" + register "generic.enable_off_delay_ms" = "30" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)" - register "generic.stop_off_delay_ms" = "2" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 10 on end + device i2c 0x10 on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" -- To view, visit https://review.coreboot.org/c/coreboot/+/77592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179df1e0e544783f77a485ad08293530e8a86ecd Gerrit-Change-Number: 77592 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/nissa/var/yaviks: Add wifi sar for yahiko
by Martin L Roth (Code Review) 02 Sep '23

02 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77585?usp=email ) Change subject: mb/google/nissa/var/yaviks: Add wifi sar for yahiko ...................................................................... mb/google/nissa/var/yaviks: Add wifi sar for yahiko Add intel wifi sar table for yahiko BUG=b:298280621 BRANCH=firmware-nissa-15217.B TEST=build, enable iwlwifi debug option, and check dmesg Change-Id: I38d2e640fc2f7cbde3986474ca1bf7de9b2d25b4 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77585 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/yaviks/variant.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/yaviks/variant.c b/src/mainboard/google/brya/variants/yaviks/variant.c index 12ca395..5c0c9ff 100644 --- a/src/mainboard/google/brya/variants/yaviks/variant.c +++ b/src/mainboard/google/brya/variants/yaviks/variant.c @@ -12,6 +12,8 @@ { if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, SAR_ID_0))) return "wifi_sar_0.hex"; + if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, SAR_ID_2))) + return "wifi_sar_2.hex"; return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/77585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d2e640fc2f7cbde3986474ca1bf7de9b2d25b4 Gerrit-Change-Number: 77585 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: add nau8318 speaker support
by Martin L Roth (Code Review) 02 Sep '23

02 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76925?usp=email ) Change subject: mb/google/brya/var/skolas: add nau8318 speaker support ...................................................................... mb/google/brya/var/skolas: add nau8318 speaker support Add variant of NAU8318(SPK) + NAU88L25B(Headphone) audio support on brya and skolas board. In fw_config settings, reuse max98360_enable_pads[] due to identical i2s configurations as nau8318. In addition, separated GPP_R7 as SPK_BEEP_EN pin. BUG=b:236561637 TEST=emerge-brya coreboot BRANCH=none Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Suggested-by: David Lin <CTLIN0(a)nuvoton.com> Signed-off-by: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/fw_config.c M src/mainboard/google/brya/variants/skolas/overridetree.cb 5 files changed, 41 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8d1600b..f0accf1 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -59,6 +59,7 @@ select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG select SOC_INTEL_RAPTORLAKE + select DRIVERS_GENERIC_NAU8315 config BOARD_GOOGLE_CRAASK bool "-> Craask" @@ -320,6 +321,7 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE + select DRIVERS_GENERIC_NAU8315 config BOARD_GOOGLE_SKOLAS4ES bool "-> Skolas4ES" diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index c2b963f..9ff3481 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -39,6 +39,10 @@ PAD_NC(GPP_R7, NONE), }; +static const struct pad_config nau8318_enable_pads[] = { + PAD_CFG_GPO(GPP_R7, 0, DEEP), /* SPK_BEEP_EN */ +}; + static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S0, NONE), PAD_NC(GPP_S1, NONE), @@ -140,12 +144,16 @@ enable_i2s(); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S))) { printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads)); printk(BIOS_INFO, "BT offload enabled\n"); gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + + if (fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S))) + gpio_configure_pads(nau8318_enable_pads, ARRAY_SIZE(nau8318_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 1884269..20d43ca 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -18,6 +18,8 @@ option MAX98373_NAU88L25B_I2S 3 option ALC1019_NAU88L25B_I2S 4 option MAX98360_ALC5682I_I2S 5 + option NAU8318_NAU88L25B_I2S 6 + end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -521,6 +523,7 @@ register "jack_eject_debounce" = "7" # 512ms device i2c 1a on probe AUDIO ALC1019_NAU88L25B_I2S + probe AUDIO NAU8318_NAU88L25B_I2S end end chip drivers/generic/alc1015 @@ -966,6 +969,14 @@ end end end + + chip drivers/generic/nau8315 + register "hid" = "NAU8318" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on + probe AUDIO NAU8318_NAU88L25B_I2S + end + end end device ref gspi1 on chip drivers/spi/acpi diff --git a/src/mainboard/google/brya/variants/skolas/fw_config.c b/src/mainboard/google/brya/variants/skolas/fw_config.c index c2b963f..9ff3481 100644 --- a/src/mainboard/google/brya/variants/skolas/fw_config.c +++ b/src/mainboard/google/brya/variants/skolas/fw_config.c @@ -39,6 +39,10 @@ PAD_NC(GPP_R7, NONE), }; +static const struct pad_config nau8318_enable_pads[] = { + PAD_CFG_GPO(GPP_R7, 0, DEEP), /* SPK_BEEP_EN */ +}; + static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S0, NONE), PAD_NC(GPP_S1, NONE), @@ -140,12 +144,16 @@ enable_i2s(); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S))) { printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads)); printk(BIOS_INFO, "BT offload enabled\n"); gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + + if (fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S))) + gpio_configure_pads(nau8318_enable_pads, ARRAY_SIZE(nau8318_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index 0f6cb86..70b0005 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -18,6 +18,7 @@ option MAX98373_NAU88L25B_I2S 3 option ALC1019_NAU88L25B_I2S 4 option MAX98360_ALC5682I_I2S 5 + option NAU8318_NAU88L25B_I2S 6 end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -521,6 +522,7 @@ register "jack_eject_debounce" = "7" # 512ms device i2c 1a on probe AUDIO ALC1019_NAU88L25B_I2S + probe AUDIO NAU8318_NAU88L25B_I2S end end chip drivers/generic/alc1015 @@ -966,6 +968,14 @@ end end end + + chip drivers/generic/nau8315 + register "hid" = "NAU8318" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on + probe AUDIO NAU8318_NAU88L25B_I2S + end + end end device ref gspi1 on chip drivers/spi/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/76925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Gerrit-Change-Number: 76925 Gerrit-PatchSet: 21 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Lin <CTLIN0(a)nuvoton.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/x86: Fixes for getting actual physical address bits
by Subrata Banik (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Cliff Huang, Jamie Ryu, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77613?usp=email ) Change subject: arch/x86: Fixes for getting actual physical address bits ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/77613/comment/b8a53545_9e4568b2 : PS1, Line 81: get_reserved_address_bits refer to https://review.coreboot.org/c/coreboot/+/77614/comment/235d45da_78fbded4/ -- To view, visit https://review.coreboot.org/c/coreboot/+/77613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Gerrit-Change-Number: 77613 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Sat, 02 Sep 2023 15:03:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add functions for getting address bits taken by MKTME
by Subrata Banik (Code Review) 02 Sep '23

02 Sep '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77614?usp=email ) Change subject: soc/intel/common: Add functions for getting address bits taken by MKTME ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/77614/comment/235d45da_78fbded4 : PS1, Line 504: get_tme_bit_size why don't you move this function as helper inside cpu_common? u can always use the TME support check and subtract the reserve range from the available size (cpu_phys_address_size()). I don't feel the need of having a weak implementation and override. -- To view, visit https://review.coreboot.org/c/coreboot/+/77614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 Gerrit-Change-Number: 77614 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Sat, 02 Sep 2023 15:02:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Fix black screen after booting to OS
by Subrata Banik (Code Review) 02 Sep '23

02 Sep '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77611?usp=email ) Change subject: soc/intel/meteorlake: Fix black screen after booting to OS ...................................................................... soc/intel/meteorlake: Fix black screen after booting to OS This patch ensures that the VR configuration for IA, SA, and GFX is properly initialized, assigning zero values to VR causes a black screen (no display) issue. Problem Statement: Override CEP (Current Excursion Protection) value with zero aka set to disable results into black screen issue (no display). Solution: Keep CEP default enabled and don't override w/ zero value. w/o this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x0 w/ this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x1 Change-Id: I8908e8b6c995390b559212d456db6ddf984448a3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eran Mitrani <mitrani(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 5 insertions(+), 4 deletions(-) Approvals: Eran Mitrani: Looks good to me, approved build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bb5b6e7..36aa11e 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -229,11 +229,12 @@ { /* FastVmode Settings for VR domains */ for (size_t domain = 0; domain < NUM_VR_DOMAINS; domain++) { - m_cfg->CepEnable[domain] = config->cep_enable[domain]; - if (m_cfg->CepEnable[domain]) { - m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain]; - if (m_cfg->EnableFastVmode[domain]) + if (config->cep_enable[domain]) { + m_cfg->CepEnable[domain] = config->cep_enable[domain]; + if (config->enable_fast_vmode[domain]) { + m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain]; m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; + } } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/77611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8908e8b6c995390b559212d456db6ddf984448a3 Gerrit-Change-Number: 77611 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cannonlake/Kconfig: Deduplicate selections
by Felix Singer (Code Review) 02 Sep '23

02 Sep '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77447?usp=email ) Change subject: soc/intel/cannonlake/Kconfig: Deduplicate selections ...................................................................... soc/intel/cannonlake/Kconfig: Deduplicate selections All of the SoCs in the cannonlake directory select the following options. So move them to the common option SOC_INTEL_CANNONLAKE_BASE in order to deduplicate selections. * FSP_USES_CB_STACK * HAVE_INTEL_FSP_REPO * SOC_INTEL_CONFIGURE_DDI_A_4_LANES Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77447 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 3 insertions(+), 9 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Elyes Haouas: Looks good to me, but someone else must approve Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b58dfd3..80237f9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -13,11 +13,13 @@ select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_STACK select GENERIC_GPIO_LIB select HAVE_DPTF_EISA_HID select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT select HAVE_HYPERTHREADING + select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -58,6 +60,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS @@ -72,30 +75,21 @@ config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK select HAVE_EXP_X86_64_SUPPORT - select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM select INTEL_CAR_NEM - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM select INTEL_CAR_NEM_ENHANCED - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO select INTEL_CAR_NEM_ENHANCED select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE_RAMTOP -- To view, visit https://review.coreboot.org/c/coreboot/+/77447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7 Gerrit-Change-Number: 77447 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoC
by Felix Singer (Code Review) 02 Sep '23

02 Sep '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77446?usp=email ) Change subject: soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoC ...................................................................... soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoC Intel Cannon Lake was removed with commit d456f65056. Thus, remove this dead code. Change-Id: I53cd9d53b01e26f530684aa9c404f50b305c1f54 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77446 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/soc/intel/cannonlake/Makefile.inc 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c747385..2a1fcee 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -85,10 +85,7 @@ bootblock-y += gpio_common.c ramstage-y += gpio_common.c -ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) -# Not yet in intel-microcode repo -#cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*) -else ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) +ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b -- To view, visit https://review.coreboot.org/c/coreboot/+/77446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53cd9d53b01e26f530684aa9c404f50b305c1f54 Gerrit-Change-Number: 77446 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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