Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email )
Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
......................................................................
Abandoned
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Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77439?usp=email )
Change subject: Documentation: Remove unused build targets
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
We might want to delete the .tex files as well if we're removing support for building them. Maybe we should see if there's still anything useful in them and turn them into markdown files? Or not. Up to you how we want to handle it. Let me know if you want me to look at changing them to markdown.
File Documentation/Makefile:
https://review.coreboot.org/c/coreboot/+/77439/comment/40287e9c_4e134370 :
PS3, Line 35: Equal to sphinx target
I might just say "Builds all documentation" so it doesn't need to be updated if we add anything else.
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Change subject: amdfwtool: Add FW type FUSE_CHAIN in the config file
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Patch Set 2:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/77506/comment/d01c0ada_69b2a615 :
PS2, Line 26: FIRMWARE_LOCATION, or SOC_NAME
Add AMD_FUSE_CHAIN here?
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77603?usp=email )
Change subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
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mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Werner Zeh: Looks good to me, approved
build bot (Jenkins): Verified
Jan Samek: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
index 430e67e..af9e25d 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cf9_reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@@ -17,4 +18,9 @@
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}
}
+
+ /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
+ and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is
+ then used on the mainboard to generate the right reset timing. */
+ outb(FULL_RST, RST_CNT);
}
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