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Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
> @Jonny, can I request you to pick CB:77616 and CB:77556 Cls and share your feedback. […]
I have verified MRC cache works both for a single socket SPR-SP and 2S SPR-SP AC.
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Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
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Patch Set 7: Code-Review+1
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Change subject: mb/google/nissa/var/pirrha: Update device configurations
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Patch Set 5: Code-Review+2
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
Patch Set 54:
(3 comments)
File src/soc/intel/common/block/cse/cse_lite_cmos.h:
https://review.coreboot.org/c/coreboot/+/74995/comment/ca042367_3d0b6229 :
PS54, Line 12: void cmos_get_curr_cse_rw_fw_version(struct fw_version *cse_version);
> wondering if we need dedicated APIs for retrieving each CMOS entries ? […]
Yes, the CMOS API design should be changed to send the entire DS to the user. This will allow the user to retrieve and operate the required CMOS entry.
The current CMOS APIs are doing exactly same, but sharing entire DS would be an improvement. I will make the changes shortly.
File src/soc/intel/common/block/cse/cse_lite_cmos.c:
https://review.coreboot.org/c/coreboot/+/74995/comment/559af3d5_fc85bf36 :
PS54, Line 74: /* Update checksum over firmware versions */
: info->crc = get_cse_info_crc(info);
> shouldn't we update the CRC after the write itself ?
The variable "info" is a temporary variable that stores the data read from the CMOS area. We update the required CSE firmware partition version, calculate the CRC checksum of the updated data, and update the CRC field. Finally, we copy the entire "info" variable to the CMOS area.
So the design is to calculate CRC locally and update it to CMOS.
https://review.coreboot.org/c/coreboot/+/74995/comment/5ca8c442_0a79c3ee :
PS54, Line 90: info->crc = get_cse_info_crc(info);
> same
The variable "info" is a temporary variable that stores the data read from the CMOS area. We update the required CSE firmware partition version, calculate the CRC checksum of the updated data, and update the CRC field. Finally, we copy the entire "info" variable to the CMOS area.
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Change subject: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77520/comment/54bea3e5_b1374db1 :
PS4, Line 11: Before root cause, this is a short term workaround to unblock function test.
> Please wrap.
Done
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Hello Eran Mitrani, Jakub Czapiga, Kane Chen, Kapil Porwal, Kun Liu, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/77520?usp=email
to look at the new patch set (#5).
Change subject: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang
......................................................................
mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang
Setting SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree can effectively
avoid the idle hang issue, but it will affect the system power.
(Before root cause, this is a short term workaround to unblock function test.)
BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang.
Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>
Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/77520/5
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Change subject: device/pci_rom: Set VBIOS checksum when filling VFCT table
......................................................................
Patch Set 1:
(1 comment)
File src/device/pci_rom.c:
https://review.coreboot.org/c/coreboot/+/77628/comment/1d361c42_b08a7e7b :
PS1, Line 254: /* Calculate checksum for VBIOS data. */
> acpi_create_vfct(), which calls pci_rom_acpi_fill_vfct(), is only called on VGA oproms with a VID = […]
Okay, I didn't realize that. If this is only for AtomBIOS ROMs, it's probably fine, but we might want to add a comment noting that it could be a problem, or maybe change the name of the function to ati_rom_acpi_fill_vfct() just so it's obvious it shouldn't ever be used for something different. I'm fine with whatever you think seems reasonable.
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