coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3824 discussions

[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
by Eric Lai (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nill Ge, Paul Menzel, Raul Rangel, Shuo Liu, Subrata Banik, TangYiwei. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email ) Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Gerrit-Change-Number: 77556 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Sep 2023 05:45:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_config
by Subrata Banik (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Chen-Tsung Hsieh, Derek Huang, Nick Vaccaro, Shon Wang, Shou-Chieh Hsu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77559?usp=email ) Change subject: mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_config ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c Gerrit-Change-Number: 77559 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 05:39:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_config
by Shon Wang (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Chen-Tsung Hsieh, Derek Huang, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77559?usp=email ) Change subject: mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_config ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: friendly ping, could you help to push CR+2. thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/77559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c Gerrit-Change-Number: 77559 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 05:37:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: {drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config
by Subrata Banik (Code Review) 04 Sep '23

04 Sep '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77616?usp=email ) Change subject: {drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config ...................................................................... {drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config This patch renames `SAVE_MRC_AFTER_FSPS` config to `FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon SP FSP implementation, where the FSP Silicon Init API produces Non-Volatile Storage (NVS) instead of the FSP-Memory Init API. According to the FSP 2.x specification (section 11.3), the FSP populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API mode. However, not all Intel SoC platforms that support the FSP 2.x specification adhere to this requirement. For example, the FSP binary for XEON SP platform produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on these platforms would result in an error. The `save_mrc_data.c` implementation provides the required hooks to locate the NVS post FSP-Silicon Init and store into Non-Volatile Storage. BUG=b:296704537 TEST=Able to build and boot Intel Xeon SP w/o any functional impact. Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/save_mrc_data.c M src/soc/intel/xeon_sp/spr/Kconfig 3 files changed, 19 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Johnny Lin: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index f5399ea..ca17bc7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -410,13 +410,26 @@ coreboot native debug driver when coreboot has integrated the debug FSP binaries. coreboot disables serial messages when this config is not enabled. -config SAVE_MRC_AFTER_FSPS +config FSP_NVS_DATA_POST_SILICON_INIT bool default n - depends on XEON_SP_COMMON_BASE help - Save MRC training data after FSP-S. Select this on platforms that generate MRC - cache HOB data as part of FSP-S rather than FSP-M. + Select this config to enable the workaround for Intel SoC platforms that + do not adhere to the FSP 2.x specification requirement, where the FSP + Silicon Init API produces Non-Volatile Storage (NVS) data instead of the + FSP-Memory Init API. + + According to the FSP 2.x specification (section 11.3), the FSP populates the + NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware + to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API + mode. + + However, not all Intel SoC platforms that support the FSP 2.x specification + adhere to this requirement. For example, the FSP binary for XEON SP platform + produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() + API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on + these platforms would result in an error. Use this config to find the NVS data + and store it in Non-Volatile Storage after the FspSiliconInit() API. config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN bool diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c index 19e8a52..1d682b9 100644 --- a/src/drivers/intel/fsp2_0/save_mrc_data.c +++ b/src/drivers/intel/fsp2_0/save_mrc_data.c @@ -46,7 +46,7 @@ * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on * a cold boot after a full firmware update. */ -#if CONFIG(SAVE_MRC_AFTER_FSPS) +#if CONFIG(FSP_NVS_DATA_POST_SILICON_INIT) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL); #else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL); diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 9c19f3b..dac093f 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -2,8 +2,8 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP bool + select FSP_NVS_DATA_POST_SILICON_INIT select MICROCODE_BLOB_NOT_HOOKED_UP - select SAVE_MRC_AFTER_FSPS select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select DISABLE_ACPI_HIBERNATE select DEFAULT_X2APIC_RUNTIME -- To view, visit https://review.coreboot.org/c/coreboot/+/77616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Gerrit-Change-Number: 77616 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang
by Subrata Banik (Code Review) 04 Sep '23

04 Sep '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77520?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang ...................................................................... mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang Setting SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree can effectively avoid the idle hang issue, but it will affect the system power. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77520 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Kun Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kane Chen: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 772ba9c5..63db4bf 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -54,6 +54,9 @@ # Temporary setting TCC of 80C = Tj max (110) - TCC_Offset (30) register "tcc_offset" = "30" + # TODO(b/287170545): workaround avoid DUT random hang + register "sagv_wp_bitmap" = "SAGV_POINTS_0_1_2" + # Enable Display Port Configuration register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, -- To view, visit https://review.coreboot.org/c/coreboot/+/77520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Gerrit-Change-Number: 77520 Gerrit-PatchSet: 6 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
by Subrata Banik (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nill Ge, Paul Menzel, Raul Rangel, Shuo Liu, TangYiwei. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email ) Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs ...................................................................... Patch Set 7: (1 comment) Patchset: PS6: > I have verified MRC cache works both for a single socket SPR-SP and 2S SPR-SP AC. Thanks Johnny. -- To view, visit https://review.coreboot.org/c/coreboot/+/77556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Gerrit-Change-Number: 77556 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Sep 2023 04:22:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch to drivers/intel: Fix misspellings & capitalization issues
by Martin L Roth (Code Review) 04 Sep '23

04 Sep '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77633?usp=email ) Change subject: arch to drivers/intel: Fix misspellings & capitalization issues ...................................................................... arch to drivers/intel: Fix misspellings & capitalization issues Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d --- M src/arch/arm64/armv8/exception.c M src/arch/x86/exception.c M src/commonlib/bsd/lz4_wrapper.c M src/commonlib/include/commonlib/coreboot_tables.h M src/commonlib/include/commonlib/loglevel.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/mp_init.c M src/device/device.c M src/device/oprom/yabel/debug.h M src/device/pci_class.c M src/device/pciexp_device.c M src/drivers/analogix/anx7625/anx7625.h M src/drivers/aspeed/common/ast_main.c M src/drivers/i2c/rtd2132/chip.h M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/ww_ring/ww_ring.c M src/drivers/i2c/ww_ring/ww_ring.h M src/drivers/i2c/ww_ring/ww_ring_programs.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/save_mrc_data.c M src/drivers/intel/gma/i915_reg.h M src/drivers/intel/gma/opregion.h M src/drivers/intel/mipi_camera/chip.h 33 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/77633/1 diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 80b619d..15d7e38 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -160,7 +160,7 @@ static int test_exception_handler(struct exc_state *state, uint64_t vector_id) { - /* Update instruction pointer to next instrution. */ + /* Update instruction pointer to next instruction. */ state->elx.elr += sizeof(uint32_t); raw_write_elr_el3(state->elx.elr); return EXC_RET_HANDLED; diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index e9234ad..e2d585f 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -305,7 +305,7 @@ int count; char ch; - /* Wishlit implement a timeout in get_packet */ + /* TODO: implement a timeout in get_packet */ do { /* wait around for the start character, ignore all other * characters diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 73a3571..efe246b 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -8,7 +8,7 @@ /* LZ4 comes with its own supposedly portable memory access functions, but they * seem to be very inefficient in practice (at least on ARM64). Since coreboot - * knows about endinaness and allows some basic assumptions (such as unaligned + * knows about endianness and allows some basic assumptions (such as unaligned * access support), we can easily write the ones we need ourselves. */ static uint16_t LZ4_readLE16(const void *src) { diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index e3e9468..d77c5eb 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -528,7 +528,7 @@ struct lb_smmstorev2 { uint32_t tag; uint32_t size; - uint32_t num_blocks; /* Number of writeable blocks in SMM */ + uint32_t num_blocks; /* Number of writable blocks in SMM */ uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ uint32_t mmap_addr; /* MMIO address of the store for read only access */ uint32_t com_buffer; /* Physical address of the communication buffer */ diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index 34d9824..79fbcfc 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -182,7 +182,7 @@ * When printing to terminals supporting ANSI escape sequences, the following * escape sequences can be printed to highlight the respective log levels * according to the BIOS_LOG_ESCAPE_PATTERN printf() pattern. At the end of a - * line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET seqence. + * line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET sequence. * * The escape sequences used here set flags with the following meanings: * 1 = bold, 4 = underlined, 5 = blinking, 7 = inverted diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d0ecd8f..e4439cd 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -295,7 +295,7 @@ /* Intel ME related timestamps */ TS_NAME_DEF(TS_ME_INFORM_DRAM_START, TS_ME_INFORM_DRAM_END, - "waiting for ME acknowledgement of raminit"), + "waiting for ME acknowledgment of raminit"), TS_NAME_DEF(TS_ME_INFORM_DRAM_END, 0, "finished waiting for ME response"), TS_NAME_DEF(TS_ME_END_OF_POST_START, TS_ME_END_OF_POST_END, "before sending EOP to ME"), TS_NAME_DEF(TS_ME_END_OF_POST_END, 0, "after sending EOP to ME"), diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 01a67fa..2bb66eb 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -33,7 +33,7 @@ timer_fsb = get_timer_fsb(); } - /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz + /* Calculate the number of ticks to run, our FSB runs at timer_fsb MHz */ ticks = usecs * timer_fsb; start = lapic_read(LAPIC_TMCCT); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 6809f81..642667b 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -777,7 +777,7 @@ size_t smsize, size_t save_state_size) { /* - * All the CPUs will relocate to permanaent handler now. Set parameters + * All the CPUs will relocate to permanent handler now. Set parameters * needed for all CPUs. The placement of each CPUs entry point is * determined by the loader. This code simply provides the beginning of * SMRAM region, the number of CPUs who will use the handler, the stack diff --git a/src/device/device.c b/src/device/device.c index 4cb0ec4..e9b8560 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -579,7 +579,7 @@ * Finalize a specific device. * * The parent should be finalized first to avoid having an ordering problem. - * This is done by calling the parent's final() method before its childrens' + * This is done by calling the parent's final() method before its children's' * final() methods. * * @param dev The device to be initialized. diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index d93fc6e..626b6c8 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -70,7 +70,7 @@ * |||||||||-DEBUG_VBE - Print messages related to VESA BIOS Extension (VBE) functions * ||||||||||-DEBUG_PRINT_INT10 - let INT10 (i.e. character output) calls print messages to Debug output * |||||||||||-DEBUG_INTR - Print messages related to interrupt handling - * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors) + * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesses to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors) * |||||||||||||-DEBUG_MEM - Print memory access made by option ROM (NOTE: this also includes accesses to fetch instructions) * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom * 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours) diff --git a/src/device/pci_class.c b/src/device/pci_class.c index c5630f7..9f2e7d6 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -93,7 +93,7 @@ { 0x02, "Multiport serial controller" }, { 0x03, "Modem" }, { 0x04, "GPIB controller" }, - { 0x05, "Smard Card controller" }, + { 0x05, "Smart Card controller" }, { 0x80, "Communication controller" } }; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 4ec6ef0..ab8430f 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -245,7 +245,7 @@ static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) { - /* check if per port clk req is supported in device */ + /* check if per port clkreq is supported in device */ u32 endp_ca; u16 lnkctl; endp_ca = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h index bba42cb..f14f8bd 100644 --- a/src/drivers/analogix/anx7625/anx7625.h +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -189,7 +189,7 @@ #define AP_AV_STATUS 0x28 #define AP_VIDEO_CHG (1<<2) #define AP_AUDIO_CHG (1<<3) -#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */ +#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: unmute */ #define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ #define AP_DISABLE_PD (1<<6) #define AP_DISABLE_DISPLAY (1<<7) diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 8dccb45..b28f6a6 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -440,7 +440,7 @@ if (ret) goto out_free; ast->vram_size = ast_get_vram_info(dev); - DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", + DRM_INFO("dram MCLK=%u MHz type=%d bus_width=%d size=%08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); } diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index b65182f..50ea7d5 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -11,7 +11,7 @@ u16 t4; /* Delay from backlight output disable to PWM output disable. */ u16 t5; /* Delay from PWM output disable to LVDS output disable. */ u16 t6; /* Delay from LVDS output disable to panel Vcc disable. */ - u16 t7; /* Delay between tweo panel power on/off sequence. */ + u16 t7; /* Delay between two panel power on/off sequence. */ /* * LVDS swap. diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 7c0c488..ff1b3a0 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -123,7 +123,7 @@ } /* - * Cr50 processes reset requests asynchronously and consceivably could be busy + * Cr50 processes reset requests asynchronously and conceivably could be busy * executing a long command and not reacting to the reset pulse for a while. * * This function will make sure that the AP does not proceed with boot until diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 98c162b..3956a19 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -310,7 +310,7 @@ } /* - * Signal Depthcharge that the controller has been initiazed by + * Signal Depthcharge that the controller has been initialized by * coreboot. */ data = LP55231_VARIABLE_COOKIE; @@ -340,7 +340,7 @@ /* * First stop all running programs to avoid - * inerference between the controllers. + * interference between the controllers. */ for (j = 0; j < WW_RING_NUM_LED_CONTROLLERS; j++) { if (!lp55231s[j].dev_addr) diff --git a/src/drivers/i2c/ww_ring/ww_ring.h b/src/drivers/i2c/ww_ring/ww_ring.h index db724d3..b43b9b8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.h +++ b/src/drivers/i2c/ww_ring/ww_ring.h @@ -5,12 +5,12 @@ /* * Different types of display patterns to be shown by the LED ring while - * contrlled by coreboot. + * controlled by coreboot. */ enum display_pattern { WWR_ALL_OFF, /* Turn the LEDs off. */ WWR_RECOVERY_PUSHED, /* Recovery button push detected on start up. */ - WWR_WIPEOUT_REQUEST, /* Held long enough for wipout request. */ + WWR_WIPEOUT_REQUEST, /* Held long enough for wipeout request. */ WWR_RECOVERY_REQUEST, /* Held long enough for recovery request. */ WWR_NORMAL_BOOT /* No buttons pressed, normal boot sequence. */ }; diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 73dd4da..da7cafc 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -89,7 +89,7 @@ * The three internal engines seem to be competing for resources and get out * of sync in seconds if left running asynchronously. * - * When solid patterns are deployed with instanteneous color intensity + * When solid patterns are deployed with instantaneous color intensity * changes, all three LEDs can be controlled by one engine in sequential * accesses. But the controllers still need to be synchronized. * diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index fb7cb85..f616d75 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -537,7 +537,7 @@ acpigen_pop_len(); /* Scope */ } -/* Emites policy definitions for each policy type */ +/* Emits policy definitions for each policy type */ static void write_policies(const struct drivers_intel_dptf_config *config) { dptf_write_enabled_policies(config->policies.active, DPTF_MAX_ACTIVE_POLICIES, diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 2f92760..69d7cf6 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -29,7 +29,7 @@ uint64_t new); void report_fsp_output(void); -/* Return version of FSP associated with fih. */ +/* Return version of FSP associated with FIH. */ static inline uint32_t fsp_version(FSP_INFO_HEADER *fih) { return fih->ImageRevision; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dd35b0f..894f9cc 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -239,7 +239,7 @@ mrc_hob = get_guid_hob(&mrc_guid, hob_list_ptr); if (mrc_hob == NULL) { printk(BIOS_DEBUG, - "Memory Configuration Data Hob not present\n"); + "Memory Configuration Data HOB not present\n"); } else { params->data_to_save = GET_GUID_HOB_DATA(mrc_hob); params->data_to_save_size = ALIGN_UP( diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index dc89064..b313711 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -85,7 +85,7 @@ if (!s3wake) mainboard_save_dimm_info(params); - /* Create romstage handof information */ + /* Create romstage handoff information */ if (romstage_handoff_init( params->power_state->prev_sleep_state == ACPI_S3) < 0) /* FIXME: A "system" reset is likely enough: */ diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index a5d55c1..5ccec59 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -207,7 +207,7 @@ gop_blt->Red = *bmp_image; break; - /* Conver 32 bit to 24bit bmp - just ignore the final byte of each pixel */ + /* Convert 32 bit to 24bit bmp - just ignore the final byte of each pixel */ case 32: gop_blt->Blue = *bmp_image++; gop_blt->Green = *bmp_image++; diff --git a/src/drivers/intel/fsp2_0/fsp_timestamp.c b/src/drivers/intel/fsp2_0/fsp_timestamp.c index c3ad331..4e50f85 100644 --- a/src/drivers/intel/fsp2_0/fsp_timestamp.c +++ b/src/drivers/intel/fsp2_0/fsp_timestamp.c @@ -32,7 +32,7 @@ } __packed; /* - * Performance Hob: + * Performance HOB: * GUID - fpdt_guid; * Data - FPDT_PEI_EXT_PERF_HEADER one or more FPDT records */ diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 0e6a39f..5339065 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -107,10 +107,10 @@ const void *hob_list; cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*cbmem_loc)); if (cbmem_loc == NULL) - die("Error: Could not add cbmem area for hob list.\n"); + die("Error: Could not add cbmem area for HOB list.\n"); hob_list = fsp_get_hob_list(); if (!hob_list) - die("Error: Could not locate hob list pointer.\n"); + die("Error: Could not locate HOB list pointer.\n"); *cbmem_loc = (uintptr_t)hob_list; } diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 9340663..b86b79b 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -123,7 +123,7 @@ if (hob->type == hob_type_names[index].type) return hob_type_names[index].name; - /* Get name for SOC specific hob */ + /* Get name for SOC specific HOB */ name = soc_get_hob_type_name(hob); if (name != NULL) return name; @@ -162,7 +162,7 @@ fsp_print_guid(BIOS_SPEW, res->owner_guid); printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); - /* Some of the SoC FSP specific hobs are of type HOB_TYPE_GUID_EXTENSION */ + /* Some of the SoC FSP specific HOBs are of type HOB_TYPE_GUID_EXTENSION */ soc_display_hob(hob); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 8fdd178..75b9ad8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -123,7 +123,7 @@ const uint8_t guid[16], const void **data, size_t *size); -/* Function to extract the FSP timestamp from FPDT Hob and display */ +/* Function to extract the FSP timestamp from FPDT HOB and display */ void fsp_display_timestamp(void); const void *fsp_get_hob_list(void); void *fsp_get_hob_list_ptr(void); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d6677b4..372e811 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -77,7 +77,7 @@ if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) do_cbmem_version_entry(cbmem_id, version); - /* Create romstage handof information */ + /* Create romstage handoff information */ romstage_handoff_init(s3wake); } diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c index 19e8a52..221f489 100644 --- a/src/drivers/intel/fsp2_0/save_mrc_data.c +++ b/src/drivers/intel/fsp2_0/save_mrc_data.c @@ -43,7 +43,7 @@ } /* - * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on + * Should be done before ramstage_cse_fw_sync() to avoid training memory twice on * a cold boot after a full firmware update. */ #if CONFIG(SAVE_MRC_AFTER_FSPS) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 377f903..8a7ccf7 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -15,7 +15,7 @@ * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory. * This is all handled in the intel-gtt.ko module. i915.ko only - * cares about the vga bit for the vga rbiter. + * cares about the vga bit for the vga arbiter. */ #define INTEL_GMCH_CTRL 0x52 #define INTEL_GMCH_VGA_DISABLE (1 << 1) @@ -1384,7 +1384,7 @@ #define SDVOC_GANG_MODE (1 << 16) #define SDVO_ENCODING_SDVO (0x0 << 10) #define SDVO_ENCODING_HDMI (0x2 << 10) -/** Requird for HDMI operation */ +/** Required for HDMI operation */ #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) #define SDVO_COLOR_RANGE_16_235 (1 << 8) #define SDVO_BORDER_ENABLE (1 << 7) @@ -1485,7 +1485,7 @@ /* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 -/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC +/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * of the infoframe structure specified by CEA-861. */ #define VIDEO_DIP_DATA_SIZE 32 @@ -1630,7 +1630,7 @@ #define BLC_HIST_CTL 0x61260 /* New registers for PCH-split platforms. Safe where new bits show up, the - * register layout machtes with gen4 BLC_PWM_CTL[12]. */ + * register layout matches with gen4 BLC_PWM_CTL[12]. */ #define BLC_PWM_CPU_CTL2 0x48250 #define BLC_PWM2_ENABLE (1UL<<31) #define BLC_PWM_CPU_CTL 0x48254 @@ -2037,7 +2037,7 @@ /** Sets the rollover for the second subcarrier phase generation DDA */ # define TV_SCDDA2_SIZE_MASK 0x7fff0000 # define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ +/** Sets the increment of the second subcarrier phase generation DDA */ # define TV_SCDDA2_INC_MASK 0x00007fff # define TV_SCDDA2_INC_SHIFT 0 @@ -2045,7 +2045,7 @@ /** Sets the rollover for the third subcarrier phase generation DDA */ # define TV_SCDDA3_SIZE_MASK 0x7fff0000 # define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ +/** Sets the increment of the third subcarrier phase generation DDA */ # define TV_SCDDA3_INC_MASK 0x00007fff # define TV_SCDDA3_INC_SHIFT 0 diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 1dd177c..7b6a85d 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -127,7 +127,7 @@ u32 aslc; /* Offset 4 ASLE interrupt command / status */ u32 tche; /* Offset 8 Technology enabled indicator */ u32 alsi; /* Offset 12 Current ALS illuminance reading */ - u32 bclp; /* Offset 16 Backlight britness to set */ + u32 bclp; /* Offset 16 Backlight brightness to set */ u32 pfit; /* Offset 20 Panel fitting Request */ u32 cblv; /* Offset 24 Brightness Current State */ u16 bclm[20]; /* Offset 28 Backlight Brightness Level Duty diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 9d8291e..95ba782 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -112,7 +112,7 @@ struct clk_config { /* IMGCLKOUT_x being used for a port */ uint8_t clknum; - /* frequency setting: 0:24Mhz, 1:19.2 Mhz */ + /* frequency setting: 0:24Mhz, 1:19.2 MHz */ uint8_t freq; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/77633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Gerrit-Change-Number: 77633 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: amdfwtool: Add FW type FUSE_CHAIN in the config file
by Bao Zheng (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel, Varshit Pandya, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77506?usp=email ) Change subject: amdfwtool: Add FW type FUSE_CHAIN in the config file ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/77506/comment/31a80fe7_627eb58c : PS2, Line 26: FIRMWARE_LOCATION, or SOC_NAME > Add AMD_FUSE_CHAIN here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Gerrit-Change-Number: 77506 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Sep 2023 03:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: amdfwtool: Add FW type FUSE_CHAIN in the config file
by Bao Zheng (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Varshit Pandya, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Varshit Pandya, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77506?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Add FW type FUSE_CHAIN in the config file ...................................................................... amdfwtool: Add FW type FUSE_CHAIN in the config file We don't have file for the fuse chain, but we need to set the level for some cases. Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/data_parse.c 3 files changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/77506/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/77506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Gerrit-Change-Number: 77506 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: chromeos/cse_board_reset.c: Clear EC AP_IDLE flag
by Derek Huang (Code Review) 04 Sep '23

04 Sep '23

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77632?usp=email ) Change subject: chromeos/cse_board_reset.c: Clear EC AP_IDLE flag ...................................................................... chromeos/cse_board_reset.c: Clear EC AP_IDLE flag When CSE jumps between RO and RW, it trigger global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=DUT boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/dedede/Kconfig.name M src/soc/intel/common/block/cse/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/clear_ec_ap_idle.c M src/vendorcode/google/chromeos/cse_board_reset.c 5 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/77632/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 10cf5e2..c8e2cc3 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -14,6 +14,7 @@ select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE + select CSE_RESET_CLEAR_EC_AP_IDLE_FLAG config BOARD_GOOGLE_DEDEDE bool "-> Dedede" @@ -208,6 +209,7 @@ select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE + select CSE_RESET_CLEAR_EC_AP_IDLE_FLAG config BOARD_GOOGLE_BOXY bool "-> Boxy" @@ -215,3 +217,4 @@ select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE + select CSE_RESET_CLEAR_EC_AP_IDLE_FLAG diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 26c623f..63011b4 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -388,4 +388,12 @@ OEM created binaries to be loaded. This binary is generated by signing with the key owned by trusted owner. +config CSE_RESET_CLEAR_EC_AP_IDLE_FLAG + bool n + default n + help + Select this if the variant is a Chromebox/base. This allows AP to direct EC + to clear AP_IDLE flag before triggering reset to make sure AP can boot up + after reset. + endif diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index dbe7545..2087097 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -14,6 +14,8 @@ ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c ramstage-$(CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG) += clear_ec_ap_idle.c +ramstage-$(CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG) += clear_ec_ap_idle.c +romstage-$(CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG) += clear_ec_ap_idle.c bootblock-y += watchdog.c verstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/clear_ec_ap_idle.c b/src/vendorcode/google/chromeos/clear_ec_ap_idle.c index 697ad23..1959a49 100644 --- a/src/vendorcode/google/chromeos/clear_ec_ap_idle.c +++ b/src/vendorcode/google/chromeos/clear_ec_ap_idle.c @@ -4,7 +4,8 @@ void clear_ec_ap_idle(void) { - if (!CONFIG(CR50_RESET_CLEAR_EC_AP_IDLE_FLAG)) + if (!CONFIG(CR50_RESET_CLEAR_EC_AP_IDLE_FLAG) && + !CONFIG(CSE_RESET_CLEAR_EC_AP_IDLE_FLAG)) return; /* Send EC command to clear AP_IDLE flag */ diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c index 08db7e2..307ece1 100644 --- a/src/vendorcode/google/chromeos/cse_board_reset.c +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -10,12 +10,15 @@ #include <intelblocks/cse.h> #include <security/tpm/tss.h> #include <vb2_api.h> +#include <vendorcode/google/chromeos/chromeos.h> void cse_board_reset(void) { int ret; struct cr50_firmware_version version; + clear_ec_ap_idle(); + if (CONFIG(TPM2) && CONFIG(TPM_GOOGLE_CR50)) { /* Initialize TPM and get the cr50 firmware version. */ ret = tlcl_lib_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/77632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Gerrit-Change-Number: 77632 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023