coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/genoa: Deal with memory map for 32M or larger flash
by Bao Zheng (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Arthur Heymans, Martin L Roth, Varshit Pandya. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76499?usp=email ) Change subject: soc/amd/genoa: Deal with memory map for 32M or larger flash ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I am wondering if this remapping is really needed. Currently only 16M of 32M is used. And all the addresses are used as relative ones. So I assume even if it is without this change, it can also boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/76499?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde Gerrit-Change-Number: 76499 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Sep 2023 08:20:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
by Bao Zheng (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Arthur Heymans, Marshall Dawson, Varshit Pandya. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76498?usp=email ) Change subject: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76498/comment/0472ea36_5a5001be : PS4, Line 75: AMD_FWM_POSITION_INDEX > this should be changed to align with […] select AMD_FWM_POSITION_x20000_DEFAULT in mainboard Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/76498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Gerrit-Change-Number: 76498 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:37:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86: Fixes for getting actual physical address bits
by Paul Menzel (Code Review) 04 Sep '23

04 Sep '23

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[L] Change in coreboot[master]: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
by Bao Zheng (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Arthur Heymans, Marshall Dawson, Varshit Pandya. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76498?usp=email ) Change subject: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76498/comment/70086ffe_05e1c650 : PS4, Line 75: AMD_FWM_POSITION_INDEX this should be changed to align with https://review.coreboot.org/c/coreboot/+/72939 -- To view, visit https://review.coreboot.org/c/coreboot/+/76498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Gerrit-Change-Number: 76498 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:29:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add functions for getting address bits taken by MKTME
by Paul Menzel (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Kane Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77614?usp=email ) Change subject: soc/intel/common: Add functions for getting address bits taken by MKTME ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77614/comment/6058bc8b_fbd68a7b : PS1, Line 15: TEST=Boot to OS and check the address bits from ACPI DMAR table Please mention the values before and after this change. File src/soc/intel/common/block/include/intelblocks/cpulib.h: https://review.coreboot.org/c/coreboot/+/77614/comment/6e0d029c_332553db : PS1, Line 221: * Can be removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/77614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 Gerrit-Change-Number: 77614 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:29:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86: Fixes for getting actual physical address bits
by Paul Menzel (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Cliff Huang, Jamie Ryu, Kane Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77613?usp=email ) Change subject: arch/x86: Fixes for getting actual physical address bits ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77613/comment/87f8eec9_af52c48b : PS1, Line 7: arch/x86: Fixes for getting actual physical address bits Please make it a statement by adding a verb (in imperative mood): > Fix getting actual physical address bits https://review.coreboot.org/c/coreboot/+/77613/comment/51c3a9f3_ed3e72d9 : PS1, Line 10: being taking being taken? https://review.coreboot.org/c/coreboot/+/77613/comment/10580066_d5e1a2d5 : PS1, Line 11: cpu_phys_address_size() is now returning the actual bits by Please add a blank line between paragraphs. File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/77613/comment/c6f412de_7f814fde : PS1, Line 49: /* : * NOTE: cpu_phys_address_size() should be called after CPU features : * has been configured, where SOC capabilities are checked and : * features are enabled in the MSRs according to the platform. For : * instance, MK-TME. Use cpu_max_phys_address_size() to get : * the maximum address bit size. : */ : int cpu_max_phys_address_size(void) : { : if (!(cpu_have_cpuid())) : return 32; : : if (cpu_cpuid_extended_level() >= 0x80000008) { : return (cpuid_eax(0x80000008) & 0xff); : } : : if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) : return 36; : return 32; : } Can this be added in a separate commit, as it is not called by anything? https://review.coreboot.org/c/coreboot/+/77613/comment/85017b15_f92c2feb : PS1, Line 73: uint32_t __weak get_reserved_address_bits(void) { return 0; } Weak functions are frowned upon in coreboot. Is it necessary? -- To view, visit https://review.coreboot.org/c/coreboot/+/77613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Gerrit-Change-Number: 77613 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add functions for getting address bits taken by MKTME
by Subrata Banik (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77614?usp=email ) Change subject: soc/intel/common: Add functions for getting address bits taken by MKTME ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/77614/comment/37780077_cb3e63be : PS1, Line 504: get_tme_bit_size > cpu_common.c only contains 'cpuid' related and does not include msr header (i.e. intel soc msr.h) and code related to msr. also, used by amd, though... is_tme_supported() supported is also a CPUID related operation hence, u can easily use inside cpu_common.c. Reg the intel specific msr inclusion, u can add those into the src/include/cpu/intel/msr.h and include inside the cpu_common.c file. Hopefully the get_tme_bit_size() is still guarded using is_tme_supported() hence, doesn't impact the AMD platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/77614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 Gerrit-Change-Number: 77614 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:23:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add functions for getting address bits taken by MKTME
by Cliff Huang (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Bora Guvendik, Jamie Ryu, Kane Chen, Subrata Banik. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77614?usp=email ) Change subject: soc/intel/common: Add functions for getting address bits taken by MKTME ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/77614/comment/b455e356_6cc1a8d8 : PS1, Line 504: get_tme_bit_size > why don't you move this function as helper inside cpu_common? […] cpu_common.c only contains 'cpuid' related and does not include msr header (i.e. intel soc msr.h) and code related to msr. also, used by amd, though... -- To view, visit https://review.coreboot.org/c/coreboot/+/77614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60e8da58fcc789e99ba93b177c1dff6b635f116 Gerrit-Change-Number: 77614 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 07:02:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/fa_ehl: Process LPDDR4 SPD files and add MT53E512M32D1NP SPD
by Jan Samek (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Uwe Poeche, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77349?usp=email ) Change subject: mb/siemens/fa_ehl: Process LPDDR4 SPD files and add MT53E512M32D1NP SPD ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I978b7450b106b86eef322df8b33df41e038599eb Gerrit-Change-Number: 77349 Gerrit-PatchSet: 6 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 06:58:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/xeon_sp: Redesign resource allocation
by Patrick Rudolph (Code Review) 04 Sep '23

04 Sep '23

Attention is currently required from: Anjaneya "Reddy" Chagam, Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Nico Huber, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67020?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Tested on SBP1 with 4 CPUs. Still works fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/67020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55c215fe078892e422a21ec1ca234faf8965542 Gerrit-Change-Number: 67020 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 04 Sep 2023 06:51:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2023