coreboot-gerrit September 2023

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78173?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/78173/1 diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index c45d8f6..5c3e90c 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -82,6 +82,16 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + #Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/78173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Gerrit-Change-Number: 78173 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Jianjun Wang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Nico Huber, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Nico Huber, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78044?usp=email to look at the new patch set (#12). Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/alderlake: Enable LZ4 compression for logo CBFS file
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78121?usp=email ) Change subject: soc/intel/alderlake: Enable LZ4 compression for logo CBFS file ...................................................................... soc/intel/alderlake: Enable LZ4 compression for logo CBFS file This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2bfb07c..c96056d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -557,4 +557,7 @@ hex default 0x8000 +config HAVE_BMP_LOGO_COMPRESS_LZMA + default n + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/78121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Gerrit-Change-Number: 78121 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Jianjun Wang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Nico Huber, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 11: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78044/comment/4d8191cb_4c5e2c89 : PS8, Line 15: split > splitting Done https://review.coreboot.org/c/coreboot/+/78044/comment/e21629f6_e86cee2c : PS8, Line 16: > is Done File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/78044/comment/bb2d9c98_f9f5edf4 : PS8, Line 130: uint32_t count > `size_t *count`. And modify it in-place. Done https://review.coreboot.org/c/coreboot/+/78044/comment/114c519a_954fc379 : PS8, Line 142: if (count >= PCIE_MAX_TRANS_TABLES) { : printk(BIOS_ERR, "%s: Not enough traslate table\n", __func__); : return -1; : } > As this is already checked in the while loop condition, this can be removed here. Done https://review.coreboot.org/c/coreboot/+/78044/comment/97668a52_c827508e : PS8, Line 166: 0x1000 > 4 * KiB Done https://review.coreboot.org/c/coreboot/+/78044/comment/82b4af6a_00fee162 : PS8, Line 171: > Move the `if (size < 0x1000)` check here, and return -1 in that case. […] Done https://review.coreboot.org/c/coreboot/+/78044/comment/9ffdc073_1075fede : PS8, Line 174: __fls > Actually, this extra `__fls` is not needed if we change the definition of `size`: […] We still need the 'size' to calculate addresses. https://review.coreboot.org/c/coreboot/+/78044/comment/e2ed94e0_1e9d050d : PS8, Line 178: write32p(table + PCIE_ATR_TRSL_PARAM_OFFSET, table_attr); > Now that this function is a bit long. Can we extract the write32p calls to a function: […] Done https://review.coreboot.org/c/coreboot/+/78044/comment/0c21a627_1ce6b5a4 : PS8, Line 181: "%s: > Align with `BIOS_INFO` above. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 11 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:19:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Jianjun Wang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel. Hello Hung-Te Lin, Nico Huber, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78044?usp=email to look at the new patch set (#11). Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 11 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Jianjun Wang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel. Hello Hung-Te Lin, Nico Huber, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78044?usp=email to look at the new patch set (#10). Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Jianjun Wang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel. Hello Hung-Te Lin, Nico Huber, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78044?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by split the MMIO space to multiple tables if its size not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78171?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... Abandoned Will submit on main -- To view, visit https://review.coreboot.org/c/coreboot/+/78171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ff78cd37f5e3ba299bb84844d897e8e05fcd568 Gerrit-Change-Number: 78171 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78172?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... Abandoned Will submit on main -- To view, visit https://review.coreboot.org/c/coreboot/+/78172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5946b570f58c904fa1884bb06ae60b8320f1addb Gerrit-Change-Number: 78172 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78172?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I5946b570f58c904fa1884bb06ae60b8320f1addb --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/78172/1 diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index c45d8f6..5c3e90c 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -82,6 +82,16 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + #Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/78172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5946b570f58c904fa1884bb06ae60b8320f1addb Gerrit-Change-Number: 78172 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2023