coreboot-gerrit September 2023

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[M] Change in coreboot[main]: mb/google/rex: Use upstream driver properties for SX9324
by Ivy Jian (Code Review) 28 Sep '23

28 Sep '23

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78174?usp=email ) Change subject: mb/google/rex: Use upstream driver properties for SX9324 ...................................................................... mb/google/rex: Use upstream driver properties for SX9324 Use human readable properties as upstream driver support. BUG=b:297977526 TEST=Able to get sensor values changed w/wo a hand covering the device. before this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { Zero, Zero, Zero }, ... Package (0x02) { "semtech,ph23-resolution", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, .... after this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { One, 0x02, 0x02 }, ... Package (0x02) { " semtech,ph23-resolution", 0x0400 }, Package (0x02) { "semtech,startup-sensor", One }, Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 47 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78174/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 1d4ba63..6442bcd 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -692,101 +692,53 @@ end end chip drivers/i2c/sx9324 - register "desc" = ""SAR1 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E00_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_gnrl_ctrl0" = "0x16" - register "reg_gnrl_ctrl1" = "0x21" - register "reg_afe_ctrl0" = "0x00" - register "reg_afe_ctrl1" = "0x10" - register "reg_afe_ctrl2" = "0x00" - register "reg_afe_ctrl3" = "0x00" - register "reg_afe_ctrl4" = "0x07" - register "reg_afe_ctrl5" = "0x00" - register "reg_afe_ctrl6" = "0x00" - register "reg_afe_ctrl7" = "0x07" - register "reg_afe_ctrl8" = "0x12" - register "reg_afe_ctrl9" = "0x0f" - register "reg_prox_ctrl0" = "0x12" - register "reg_prox_ctrl1" = "0x12" - register "reg_prox_ctrl2" = "0x90" - register "reg_prox_ctrl3" = "0x60" - register "reg_prox_ctrl4" = "0x0c" - register "reg_prox_ctrl5" = "0x12" - register "reg_prox_ctrl6" = "0x3c" - register "reg_prox_ctrl7" = "0x58" - register "reg_adv_ctrl0" = "0x00" - register "reg_adv_ctrl1" = "0x00" - register "reg_adv_ctrl2" = "0x00" - register "reg_adv_ctrl3" = "0x00" - register "reg_adv_ctrl4" = "0x00" - register "reg_adv_ctrl5" = "0x05" - register "reg_adv_ctrl6" = "0x00" - register "reg_adv_ctrl7" = "0x00" - register "reg_adv_ctrl8" = "0x00" - register "reg_adv_ctrl9" = "0x00" - register "reg_adv_ctrl10" = "0x5c" - register "reg_adv_ctrl11" = "0x52" - register "reg_adv_ctrl12" = "0xb5" - register "reg_adv_ctrl13" = "0x00" - register "reg_adv_ctrl14" = "0x80" - register "reg_adv_ctrl15" = "0x0c" - register "reg_adv_ctrl16" = "0x38" - register "reg_adv_ctrl17" = "0x56" - register "reg_adv_ctrl18" = "0x33" - register "reg_adv_ctrl19" = "0xf0" - register "reg_adv_ctrl20" = "0xf0" - device i2c 28 on end - end - chip drivers/i2c/sx9324 - register "desc" = ""SAR2 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E08_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "2" - register "reg_gnrl_ctrl0" = "0x16" - register "reg_gnrl_ctrl1" = "0x21" - register "reg_afe_ctrl0" = "0x00" - register "reg_afe_ctrl1" = "0x10" - register "reg_afe_ctrl2" = "0x00" - register "reg_afe_ctrl3" = "0x00" - register "reg_afe_ctrl4" = "0x07" - register "reg_afe_ctrl5" = "0x00" - register "reg_afe_ctrl6" = "0x00" - register "reg_afe_ctrl7" = "0x07" - register "reg_afe_ctrl8" = "0x12" - register "reg_afe_ctrl9" = "0x0f" - register "reg_prox_ctrl0" = "0x12" - register "reg_prox_ctrl1" = "0x12" - register "reg_prox_ctrl2" = "0x90" - register "reg_prox_ctrl3" = "0x60" - register "reg_prox_ctrl4" = "0x0c" - register "reg_prox_ctrl5" = "0x12" - register "reg_prox_ctrl6" = "0x3c" - register "reg_prox_ctrl7" = "0x58" - register "reg_adv_ctrl0" = "0x00" - register "reg_adv_ctrl1" = "0x00" - register "reg_adv_ctrl2" = "0x00" - register "reg_adv_ctrl3" = "0x00" - register "reg_adv_ctrl4" = "0x00" - register "reg_adv_ctrl5" = "0x05" - register "reg_adv_ctrl6" = "0x00" - register "reg_adv_ctrl7" = "0x00" - register "reg_adv_ctrl8" = "0x00" - register "reg_adv_ctrl9" = "0x00" - register "reg_adv_ctrl10" = "0x5c" - register "reg_adv_ctrl11" = "0x52" - register "reg_adv_ctrl12" = "0xb5" - register "reg_adv_ctrl13" = "0x00" - register "reg_adv_ctrl14" = "0x80" - register "reg_adv_ctrl15" = "0x0c" - register "reg_adv_ctrl16" = "0x38" - register "reg_adv_ctrl17" = "0x56" - register "reg_adv_ctrl18" = "0x33" - register "reg_adv_ctrl19" = "0xf0" - register "reg_adv_ctrl20" = "0xf0" - device i2c 2C on end - end + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E00_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "ph0_pin" = "{1, 2, 2}" + register "ph1_pin" = "{2, 1, 2}" + register "ph2_pin" = "{2, 2, 1}" + register "ph3_pin" = "{2, 1, 1}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "2" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe CELLULAR CELLULAR_USB + probe CELLULAR CELLULAR_PCIE + end + end + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E08_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "ph0_pin" = "{1, 2, 2}" + register "ph1_pin" = "{2, 1, 2}" + register "ph2_pin" = "{2, 2, 1}" + register "ph3_pin" = "{2, 1, 1}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "2" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 2c on + probe CELLULAR CELLULAR_USB + probe CELLULAR CELLULAR_PCIE + end + end end #I2C5 device ref pcie_rp5 on probe WIFI WIFI_PCIE -- To view, visit https://review.coreboot.org/c/coreboot/+/78174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Gerrit-Change-Number: 78174 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/cmn/gfx: Add API to report presence of external display
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78080?usp=email ) Change subject: soc/intel/cmn/gfx: Add API to report presence of external display ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/78080/comment/77bba6be_48376b40 : PS1, Line 59: #if CONFIG(REPORT_EXTERNAL_DISPLAY_AT_PREBOOT) > So you're saying that those other platforms would return 0 from report_external_display() (because they would always initialize the eDP display), which is the same as the stub function you implemented for when the Kconfig is disabled? Sounds like that would work fine to me. yes, your understanding is correct > The point is to just reduce the number of Kconfig options and special cases to keep track of, to make the code easier to follow. Especially if this only affects older boards and we're planning to have the external display initialization in that case for all future devices, I don't think there's a problem with making some older platforms read a few pointless (but harmless) registers, if it helps simplify things a bit. I'm not sure if it's harmless bt I can seek some help from community to test this code on SKL and other generations like JSL etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/78080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Gerrit-Change-Number: 78080 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 07:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yu-Ping Wu (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 12: (3 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/78044/comment/c9b4931e_f980276e : PS8, Line 174: __fls > We still need the 'size' to calculate addresses. Right. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/78044/comment/452ae6ed_d9e9748b : PS12, Line 167: while (remaining && *count < PCIE_MAX_TRANS_TABLES) { Add comment ``` /* The table size needs to be a power of 2. In addition, cpu_addr needs to be aligned to the size. */ ``` https://review.coreboot.org/c/coreboot/+/78044/comment/0bac00eb_b1412f36 : PS12, Line 175: remaining table -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:59:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Sukumar Ghorai, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 4: (3 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/bfe5269b_3aa6b622 : PS4, Line 456: CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC CONFIG(SOC_INTEL_SLP_S0_FREQ_TSC) https://review.coreboot.org/c/coreboot/+/78164/comment/7110521d_eebf0220 : PS4, Line 461: another thought why not set the macro based on the CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC value? and default value for CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC is zero unless overrides by the SoC Kconfig ? #define ACPI_LPIT_CTR_FREQ_TSC CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC File src/soc/intel/common/block/acpi/lpit.c: https://review.coreboot.org/c/coreboot/+/78164/comment/d17abf85_8aef37f2 : PS3, Line 34: MSR value return in usec > MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we must not apply the TSC frequency, are you saying the value should be in usec hence it's better to set it zero ? if yes, then why are you overriding this macro ACPI_LPIT_CTR_FREQ_TSC using Kconfig ? https://review.coreboot.org/c/coreboot/+/78164/4/src/include/acpi/acpi.h#457 looking at the overrides in rex (MTL). I'm confused and need to understand things better 1. setting ACPI_LPIT_CTR_FREQ_TSC based on kconfig should be managed in different CL 2. MTL overriding ACPI_LPIT_CTR_FREQ_TSC using Kconfig 3. who is the user of ACPI_LPIT_CTR_FREQ_TSC if you are hardcoding the counter_frequency to zero. -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:58:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/siemens: Move selects from Kconfig.name to Kconfig
by Mario Scheithauer (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Felix Singer, Jan Samek. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75078?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/siemens: Move selects from Kconfig.name to Kconfig ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/mainboard/siemens/mc_apl1/Kconfig: https://review.coreboot.org/c/coreboot/+/75078/comment/551b0e53_dcd3d996 : PS5, Line 10: config BOARD_SIEMENS_MC_APL1 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL2 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL3 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL4 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL5 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL6 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL7 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 Isn't it then perhaps better to select _BASEBOARD_ in variant/../Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/75078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2 Gerrit-Change-Number: 75078 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreen
by Derek Huang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Chen-Tsung Hsieh, Nick Vaccaro, Shon Wang, Shou-Chieh Hsu, Subrata Banik. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77996?usp=email ) Change subject: mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreen ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Gerrit-Change-Number: 77996 Gerrit-PatchSet: 6 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:43:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Derek Huang (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Joey Peng. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78144?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Gerrit-Change-Number: 78144 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:42:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78173?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... Abandoned Will submit on main -- To view, visit https://review.coreboot.org/c/coreboot/+/78173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Gerrit-Change-Number: 78173 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Joey Peng (Code Review) 28 Sep '23

28 Sep '23

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78144?usp=email ) Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78144/1 diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index c45d8f6..5c3e90c 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -82,6 +82,16 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + #Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/78144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Gerrit-Change-Number: 78144 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: ec/google: Assume LID open for platforms without VBOOT_LID_SWITCH
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78077?usp=email ) Change subject: ec/google: Assume LID open for platforms without VBOOT_LID_SWITCH ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78077/comment/5b93c21d_59618f1b : PS1, Line 7: Assume LID open for platforms without VBOOT_LID_SWITCH > How about detachables? I saw all the chromeos devices are selecting VBOOT_LID_SWITCH config. the only exception (which i have landed) is for Ovis (a chromebox hence, doesn't req to select VBOOT_LID_SWITCH config) -- To view, visit https://review.coreboot.org/c/coreboot/+/78077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34bfc21329660a4bfd1ffed939b6dfb7e7109204 Gerrit-Change-Number: 78077 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 06:28:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2023