coreboot-gerrit September 2023

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add PsysPmax configuration
by Jakub Czapiga (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Martin L Roth, Paul Menzel, Subrata Banik, Tarun, Tarun Tuli. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76796?usp=email ) Change subject: soc/intel/meteorlake: Add PsysPmax configuration ...................................................................... Patch Set 10: (2 comments) File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/76796/comment/2b83d82a_a61fedae : PS10, Line 450: /* Platform Power Pmax in Watts */ > Add comment about 0 being automatic? Done https://review.coreboot.org/c/coreboot/+/76796/comment/db461139_3f4dbdf1 : PS10, Line 451: psys_pmax > Maybe change to psys_pmax_watts? Then the unit is obvious in devicetree. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Gerrit-Change-Number: 76796 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 13:59:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add PsysPmax configuration
by Jakub Czapiga (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, Tarun Tuli. Hello Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76796?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake: Add PsysPmax configuration ...................................................................... soc/intel/meteorlake: Add PsysPmax configuration psys_pmax_watts is configured in SoC node of devicetree. Value represents Watts the PSU provides. Zero means automatic/default configuration (not optimal). BUG=b:289853442 TEST=Build google/rex/ovis4es target board Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/76796/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/76796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Gerrit-Change-Number: 76796 Gerrit-PatchSet: 11 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/rex/var/ovis: Add DPTF configuration
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77623?usp=email ) Change subject: mb/google/rex/var/ovis: Add DPTF configuration ...................................................................... mb/google/rex/var/ovis: Add DPTF configuration Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 67 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 17d75cb..2c49c4c 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -53,6 +53,73 @@ device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 28000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 64000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/77623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Gerrit-Change-Number: 77623 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Add chipset.cb
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78082?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add chipset.cb ...................................................................... soc/amd/genoa: Add chipset.cb Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Signed-off-by: vbpandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/chipset.cb 2 files changed, 225 insertions(+), 0 deletions(-) Approvals: Martin Roth: Looks good to me, approved build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index f799ac18..0331e36 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -19,6 +19,10 @@ config USE_EXP_X86_64_SUPPORT default y +config CHIPSET_DEVICETREE + string + default "soc/amd/genoa/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x7000000 diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb new file mode 100644 index 0000000..6523617 --- /dev/null +++ b/src/soc/amd/genoa/chipset.cb @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/genoa + device cpu_cluster 0 on + end + + device domain 0 on + device pci 00.0 alias gnb_0 on end + device pci 00.2 alias iommu_0 off end + device pci 00.3 alias rcec_0 off end + + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_0_0_a off end + device pci 01.2 alias gpp_bridge_0_1_a off end + device pci 01.3 alias gpp_bridge_0_2_a off end + device pci 01.4 alias gpp_bridge_0_3_a off end + device pci 01.5 alias gpp_bridge_0_4_a off end + device pci 01.6 alias gpp_bridge_0_5_a off end + device pci 01.7 alias gpp_bridge_0_6_a off end + + device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.1 alias gpp_bridge_0_7_a off end + device pci 02.2 alias gpp_bridge_0_8_a off end + + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 alias gpp_bridge_0_0_b off end + device pci 03.2 alias gpp_bridge_0_1_b off end + device pci 03.3 alias gpp_bridge_0_2_b off end + device pci 03.4 alias gpp_bridge_0_3_b off end + device pci 03.5 alias gpp_bridge_0_4_b off end + device pci 03.6 alias gpp_bridge_0_5_b off end + device pci 03.7 alias gpp_bridge_0_6_b off end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 alias gpp_bridge_0_7_b off end + device pci 04.2 alias gpp_bridge_0_8_b off end + + device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.1 alias gpp_bridge_0_0_c off end + device pci 05.2 alias gpp_bridge_0_1_c off end + device pci 05.3 alias gpp_bridge_0_2_c off end + device pci 05.4 alias gpp_bridge_0_3_c off end + + device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 + device pci 0.0 off end # Dummy PCIe function + device pci 0.1 off end + device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge + device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB + device pci 0.4 alias xhci_0 off end # USB + device pci 0.5 alias mp0_0 off end # PSP (MP0) + device pci 0.6 alias acp_0 off end # Audio Processor (ACP) + device pci 0.7 alias hda_0 off end # Audio Processor HD Audio Controller (main AZ) + end + device pci 07.2 alias gpp_bridge_0_b off # Internal GPP Bridge 1 to Bus C0 + device pci 0.0 alias sata_0_0 off end # first SATA controller; AHCI mode + device pci 0.1 alias sata_0_1 off end # second SATA controller; AHCI mode + end + + device pci 14.0 alias smbus on end # primary FCH function + device pci 14.3 alias lpc_bridge on end + device pci 14.6 alias sdhci off end + + device pci 18.0 alias data_fabric_0 on end + device pci 18.1 alias data_fabric_1 on end + device pci 18.2 alias data_fabric_2 on end + device pci 18.3 alias data_fabric_3 on end + device pci 18.4 alias data_fabric_4 on end + device pci 18.5 alias data_fabric_5 on end + device pci 18.6 alias data_fabric_6 on end + device pci 18.7 alias data_fabric_7 on end + end + + device domain 1 on + device pci 00.0 alias gnb_1 on end + device pci 00.2 alias iommu_1 off end + device pci 00.3 alias rcec_1 off end + + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_1_0_a off end + device pci 01.2 alias gpp_bridge_1_1_a off end + device pci 01.3 alias gpp_bridge_1_2_a off end + device pci 01.4 alias gpp_bridge_1_3_a off end + device pci 01.5 alias gpp_bridge_1_4_a off end + device pci 01.6 alias gpp_bridge_1_5_a off end + device pci 01.7 alias gpp_bridge_1_6_a off end + + device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.1 alias gpp_bridge_1_7_a off end + device pci 02.2 alias gpp_bridge_1_8_a off end + + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 alias gpp_bridge_1_0_b off end + device pci 03.2 alias gpp_bridge_1_1_b off end + device pci 03.3 alias gpp_bridge_1_2_b off end + device pci 03.4 alias gpp_bridge_1_3_b off end + device pci 03.5 alias gpp_bridge_1_4_b off end + device pci 03.6 alias gpp_bridge_1_5_b off end + device pci 03.7 alias gpp_bridge_1_6_b off end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 alias gpp_bridge_1_7_b off end + device pci 04.2 alias gpp_bridge_1_8_b off end + + device pci 05.0 on end # Dummy Host Bridge, do not disable + + device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.1 alias gpp_bridge_1_a off + device pci 0.0 off end # Dummy PCIe function + device pci 0.1 off end #SDXI + end + end + + device domain 2 on + device pci 00.0 alias gnb_2 on end + device pci 00.2 alias iommu_2 off end + device pci 00.3 alias rcec_2 off end + + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_2_0_a off end + device pci 01.2 alias gpp_bridge_2_1_a off end + device pci 01.3 alias gpp_bridge_2_2_a off end + device pci 01.4 alias gpp_bridge_2_3_a off end + device pci 01.5 alias gpp_bridge_2_4_a off end + device pci 01.6 alias gpp_bridge_2_5_a off end + device pci 01.7 alias gpp_bridge_2_6_a off end + + device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.1 alias gpp_bridge_2_7_a off end + device pci 02.2 alias gpp_bridge_2_8_a off end + + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 alias gpp_bridge_2_0_b off end + device pci 03.2 alias gpp_bridge_2_1_b off end + device pci 03.3 alias gpp_bridge_2_2_b off end + device pci 03.4 alias gpp_bridge_2_3_b off end + device pci 03.5 alias gpp_bridge_2_4_b off end + device pci 03.6 alias gpp_bridge_2_5_b off end + device pci 03.7 alias gpp_bridge_2_6_b off end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 alias gpp_bridge_2_7_b off end + device pci 04.2 alias gpp_bridge_2_8_b off end + + device pci 05.0 on end # Dummy Host Bridge, do not disable + + device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.1 alias gpp_bridge_2_a off + device pci 0.0 off end # Dummy PCIe function + device pci 0.1 off end + end + end + + device domain 3 on + device pci 00.0 alias gnb_3 on end + device pci 00.2 alias iommu_3 off end + device pci 00.3 alias rcec_3 off end + + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_3_0_a off end + device pci 01.2 alias gpp_bridge_3_1_a off end + device pci 01.3 alias gpp_bridge_3_2_a off end + device pci 01.4 alias gpp_bridge_3_3_a off end + device pci 01.5 alias gpp_bridge_3_4_a off end + device pci 01.6 alias gpp_bridge_3_5_a off end + device pci 01.7 alias gpp_bridge_3_6_a off end + + device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.1 alias gpp_bridge_3_7_a off end + device pci 02.2 alias gpp_bridge_3_8_a off end + + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 alias gpp_bridge_3_0_b off end + device pci 03.2 alias gpp_bridge_3_1_b off end + device pci 03.3 alias gpp_bridge_3_2_b off end + device pci 03.4 alias gpp_bridge_3_3_b off end + device pci 03.5 alias gpp_bridge_3_4_b off end + device pci 03.6 alias gpp_bridge_3_5_b off end + device pci 03.7 alias gpp_bridge_3_6_b off end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 alias gpp_bridge_3_7_b off end + device pci 04.2 alias gpp_bridge_3_8_b off end + + device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.1 alias gpp_bridge_3_0_c off end + device pci 05.2 alias gpp_bridge_3_1_c off end + device pci 05.3 alias gpp_bridge_3_2_c off end + device pci 05.4 alias gpp_bridge_3_3_c off end + + device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.1 alias gpp_bridge_3_a off + device pci 0.0 off end # Dummy PCIe function + device pci 0.1 off end #SDXI + device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge + device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB + device pci 0.4 alias xhci_3 off end # USB + device pci 0.5 alias mp0_3 off end # PSP (MP0) + end + + device pci 07.2 alias gpp_bridge_3b off + device pci 0.0 alias sata_3_0 off end # first SATA controller; AHCI mode + device pci 0.1 alias sata_3_1 off end # second SATA controller; AHCI mode + end + end + + device mmio 0xfedc2000 alias i2c_0 off end + device mmio 0xfedc3000 alias i2c_1 off end + device mmio 0xfedc4000 alias i2c_2 off end + device mmio 0xfedc5000 alias i2c_3 off end + device mmio 0xfedc6000 alias i2c_4 off end + device mmio 0xfedc7000 alias i2c_5 off end + device mmio 0xfedc9000 alias uart_0 off end + device mmio 0xfedca000 alias uart_1 off end + device mmio 0xfedce000 alias uart_2 off end + device mmio 0xfedd2600 alias i3c_0 off end + device mmio 0xfedd3600 alias i3c_1 off end + device mmio 0xfedd4600 alias i3c_2 off end + device mmio 0xfedd5600 alias i3c_3 off end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/78082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Gerrit-Change-Number: 78082 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: payloads/edk2: Update default branch for MrChromebox repo to 2023-09
by Sean Rhodes (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78136?usp=email ) Change subject: payloads/edk2: Update default branch for MrChromebox repo to 2023-09 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c5f9ae1ca4edd8211f55f4ecf2b3b495f473a43 Gerrit-Change-Number: 78136 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 13:16:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punct
by Matt DeVillier (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jonathon Hall, Lance Zhao. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78095?usp=email ) Change subject: acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punct ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Patchset: PS2: > A keymap was necessary so osk-sdl doesn't think the PS/2 keyboard is a "full keyboard" - it shows th […] ack File src/include/acpi/acpigen_ps2_keybd.h: https://review.coreboot.org/c/coreboot/+/78095/comment/bf89906e_28b7a16d : PS2, Line 39: has_alpha_num_punct_keys > Personally I like `has_alpha_num_punct_keys` because it is more precise, the meaning of "full keyboa […] nah, works for me -- To view, visit https://review.coreboot.org/c/coreboot/+/78095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Gerrit-Change-Number: 78095 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 13:14:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 6: (3 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74874/comment/e70b9427_9f0d07ea : PS6, Line 1077: printk(BIOS_INFO, "Check if PSR is supported in this SKU !\n"); same https://review.coreboot.org/c/coreboot/+/74874/comment/f033dbb3_98a3a504 : PS6, Line 1090: printk(BIOS_DEBUG, "PSR is supported in this SKU !\n"); we don't need such prints https://review.coreboot.org/c/coreboot/+/74874/comment/28a52c74_94b16251 : PS6, Line 1106: shouldn't we check this at line #1100 ? what is the boot time impact ? care to add a timestamp ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 09:43:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Eran Mitrani, Hannah Williams, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Rizwan Qureshi, Tarun, Tarun Tuli, sridhar siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76115?usp=email ) Change subject: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/76115/comment/0348f4ab_41b9ac80 : PS11, Line 29: select SOC_INTEL_CSE_LITE_PSR > agreed . that was the reason in my patch i call this just before issuing backup PSR command, so we do a switch only when we are in downgrade scenario. have you filed a bug already for CSE? if not please raise a partner bug to track this part. This is not an improvement for say. I'm marking this resolve w/ understanding that sending PSR backup cmd for non-vpro sku is harmless. btw, please take a look into below comments as well. https://review.coreboot.org/c/coreboot/+/74577/comment/659d6050_b159441d/ -- To view, visit https://review.coreboot.org/c/coreboot/+/76115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39af029a5f0c018a5db3ac68191764abfa9518ac Gerrit-Change-Number: 76115 Gerrit-PatchSet: 13 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 09:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cse: Back up PSR data during CSE FW downgrade
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Paul Menzel, Rizwan Qureshi, sridhar siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577?usp=email ) Change subject: soc/intel/cse: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 52: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/659d6050_b159441d : PS52, Line 1115: if (backup_psr_resp.status != PSR_STATUS_SUCCESS) thinking loud here, won't we run into this case while sending PSR backup for non-vpro sku ? based on the discussion that we have, we can't mark PSR_BACKUP_DONE even for case where PSR back is unsupported for a non-vpro sku. -- To view, visit https://review.coreboot.org/c/coreboot/+/74577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 52 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 09:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Kapil Porwal (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Subrata Banik, Sukumar Ghorai, Tarun. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 4: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/0d261a65_2296260d : PS4, Line 456: _TSC `TSC` is one of the option (0 means TSC), right? -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 09:36:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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