coreboot-gerrit September 2023

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[M] Change in coreboot[main]: soc/amd/genoa/southbridge.h: Add PM related macros
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76502?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa/southbridge.h: Add PM related macros ...................................................................... soc/amd/genoa/southbridge.h: Add PM related macros All verified with PPR. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: If288079310ba74333f04173978f6a123ce95f4d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/genoa/include/soc/southbridge.h 1 file changed, 109 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/genoa/include/soc/southbridge.h b/src/soc/amd/genoa/include/soc/southbridge.h index 95c054c..148ebfc 100644 --- a/src/soc/amd/genoa/include/soc/southbridge.h +++ b/src/soc/amd/genoa/include/soc/southbridge.h @@ -5,6 +5,115 @@ #include <soc/iomap.h> +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_ISACONTROL 0x04 +#define ABCLKGATEEN BIT(16) +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_SERIRQ_CONF 0x54 +#define PM_SERIRQ_NUM_BITS_17 0x0000 +#define PM_SERIRQ_NUM_BITS_18 0x0004 +#define PM_SERIRQ_NUM_BITS_19 0x0008 +#define PM_SERIRQ_NUM_BITS_20 0x000c +#define PM_SERIRQ_NUM_BITS_21 0x0010 +#define PM_SERIRQ_NUM_BITS_22 0x0014 +#define PM_SERIRQ_NUM_BITS_23 0x0018 +#define PM_SERIRQ_NUM_BITS_24 0x001c +#define PM_SERIRQ_MODE BIT(6) +#define PM_SERIRQ_ENABLE BIT(7) +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) +#define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) +#define PM_SPI_PAD_PU_PD 0x90 +#define PM_ESPI_CS_USE_DATA2 BIT(16) +#define PM_LPC_GATING 0xec +#define PM_LPC_AB_NO_BYPASS_EN BIT(2) +#define PM_LPC_A20_EN BIT(1) +#define PM_LPC_ENABLE BIT(0) + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ + +/* FCH MISC Registers 0xfed80e00 */ +#define GPP_CLK_CNTRL 0x00 +#define GPP_CLK0_REQ_SHIFT 0 +#define GPP_CLK1_REQ_SHIFT 2 +#define GPP_CLK4_REQ_SHIFT 4 +#define GPP_CLK2_REQ_SHIFT 6 +#define GPP_CLK3_REQ_SHIFT 8 +#define GPP_CLK5_REQ_SHIFT 10 +#define GPP_CLK6_REQ_SHIFT 12 +#define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_OUTPUT_AVAILABLE 4 +#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) +#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) + +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S0I3_TURNOFF_EN BIT(19) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10) +#define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) +#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ void fch_pre_init(void); void fch_early_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/76502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If288079310ba74333f04173978f6a123ce95f4d9 Gerrit-Change-Number: 76502 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Add timer & tsc support
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76501?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add timer & tsc support ...................................................................... soc/amd/genoa: Add timer & tsc support Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/include/soc/msr.h D src/soc/amd/genoa/timer.c 4 files changed, 43 insertions(+), 10 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 7ef5707..b73b53c 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -8,13 +8,13 @@ select ARCH_X86 select HAVE_EXP_X86_64_SUPPORT select NO_ECAM_MMCONF_SUPPORT - select NO_MONOTONIC_TIMER select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select UNKNOWN_TSC_RATE + select SOC_AMD_COMMON_BLOCK_TSC select X86_CUSTOM_BOOTMEDIA config USE_EXP_X86_64_SUPPORT diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 0e08ac6..56a98e6 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -9,7 +9,6 @@ romstage-y += romstage.c ramstage-y += chip.c -ramstage-y += timer.c CPPFLAGS_common += -I$(src)/soc/amd/genoa/include diff --git a/src/soc/amd/genoa/include/soc/msr.h b/src/soc/amd/genoa/include/soc/msr.h new file mode 100644 index 0000000..368c631 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/msr.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_MSR_H +#define AMD_GENOA_MSR_H + +/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ +union pstate_msr { + struct { + uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */ + uint64_t cpu_dfs_id : 6; /* [ 8..13] */ + uint64_t cpu_vid_0_7 : 8; /* [14..21] */ + uint64_t idd_value : 8; /* [22..29] */ + uint64_t idd_div : 2; /* [30..31] */ + uint64_t cpu_vid_8 : 1; /* [32..32] */ + uint64_t : 30; /* [33..62] */ + uint64_t pstate_en : 1; /* [63..63] */ + }; + uint64_t raw; +}; + + +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define MSR_CPPC_CAPABILITY_1 0xc00102b0 +#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 +#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 +#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 +#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 + +#define MSR_CPPC_ENABLE 0xc00102b1 +#define MSR_CPPC_REQUEST 0xc00102b3 +#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 +#define SHIFT_CPPC_REQUEST_DES_PERF 16 +#define SHIFT_CPPC_REQUEST_MIN_PERF 8 +#define SHIFT_CPPC_REQUEST_MAX_PERF 0 + +#define MSR_CPPC_STATUS 0xc00102b4 + +#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 +#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 + +#endif /* AMD_GENOA_MSR_H */ diff --git a/src/soc/amd/genoa/timer.c b/src/soc/amd/genoa/timer.c deleted file mode 100644 index 9054ffd..0000000 --- a/src/soc/amd/genoa/timer.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <delay.h> - -void init_timer(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/76501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb Gerrit-Change-Number: 76501 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/genoa: Add function to fetch common code dt configuration
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76500?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add function to fetch common code dt configuration ...................................................................... soc/amd/genoa: Add function to fetch common code dt configuration Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: I5d5d3ff27ab0953844f9bbef30b6487fb480e29b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76500 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/chip.h A src/soc/amd/genoa/config.c 3 files changed, 25 insertions(+), 0 deletions(-) Approvals: Martin Roth: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 164c5e9..0e08ac6 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_AMD_GENOA),y) all-y += mmap_boot.c +all-y += config.c bootblock-y += early_fch.c diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h new file mode 100644 index 0000000..9168586 --- /dev/null +++ b/src/soc/amd/genoa/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GENOA_CHIP_H__ +#define __GENOA_CHIP_H__ + +#include <amdblocks/chip.h> + +struct soc_amd_genoa_config { + struct soc_amd_common_config common_config; +}; + +#endif diff --git a/src/soc/amd/genoa/config.c b/src/soc/amd/genoa/config.c new file mode 100644 index 0000000..f59964a --- /dev/null +++ b/src/soc/amd/genoa/config.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <amdblocks/chip.h> +#include <device/device.h> +#include "chip.h" + +const struct soc_amd_common_config *soc_get_common_config(void) +{ + const struct soc_amd_genoa_config *cfg = config_of_soc(); + return &cfg->common_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d5d3ff27ab0953844f9bbef30b6487fb480e29b Gerrit-Change-Number: 76500 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/genoa: Deal with memory map for 32M or larger flash
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76499?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Deal with memory map for 32M or larger flash ...................................................................... soc/amd/genoa: Deal with memory map for 32M or larger flash Only the lower half of the flash gets memory mapped below 4G in the current setup. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/76499 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/mmap_boot.c 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 705805e..7ef5707 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -15,6 +15,7 @@ select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select UNKNOWN_TSC_RATE + select X86_CUSTOM_BOOTMEDIA config USE_EXP_X86_64_SUPPORT default y diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index de996d6..164c5e9 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_GENOA),y) +all-y += mmap_boot.c + bootblock-y += early_fch.c romstage-y += romstage.c diff --git a/src/soc/amd/genoa/mmap_boot.c b/src/soc/amd/genoa/mmap_boot.c new file mode 100644 index 0000000..d29af41 --- /dev/null +++ b/src/soc/amd/genoa/mmap_boot.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> +#include <endian.h> +#include <spi_flash.h> + +#if CONFIG_ROM_SIZE >= (16 * MiB) +#define ROM_SIZE (16 * MiB) +#else +#define ROM_SIZE CONFIG_ROM_SIZE +#endif + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base ((void *)(uintptr_t)(0x100000000ULL-ROM_SIZE)) + +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(rom_base, ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + table->flash_base = 0; + table->host_base = (uint32_t)(uintptr_t)rom_base; + table->size = ROM_SIZE; + + return 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76499?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde Gerrit-Change-Number: 76499 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76498?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add Kconfig/Makefile to generate PSP image ...................................................................... soc/amd/genoa: Add Kconfig/Makefile to generate PSP image TESTED: AMD onyx reaches x86 code Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/amd/onyx/Makefile.inc M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/fw.cfg 4 files changed, 244 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/onyx/Makefile.inc b/src/mainboard/amd/onyx/Makefile.inc new file mode 100644 index 0000000..323f9ee --- /dev/null +++ b/src/mainboard/amd/onyx/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin +APCB_SOURCES1 = $(MAINBOARD_BLOBS_DIR)/Typex60_0_1_0_Apcb.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/Typex68_0_0_0_ApcbRec.bin +APCB_SOURCES_RECOVERY1 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_8_0_ApcbRec.bin +APCB_SOURCES_RECOVERY2 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_9_0_ApcbRec.bin +else +files_added:: warn_no_apcb +endif diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 0331e36..705805e 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -74,4 +74,62 @@ help Sets the size of DRAM allocation for romstage in linker script. -endif +menu "PSP Configuration Options" + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/genoa/fw.cfg" + +config PSP_DISABLE_POSTCODES + bool "Disable PSP post codes" + help + Disables the output of port80 post codes from PSP. + +config PSP_INIT_ESPI + bool "Initialize eSPI in PSP Stage 2 Boot Loader" + help + Select to initialize the eSPI controller in the PSP Stage 2 Boot + Loader. + +config PSP_UNLOCK_SECURE_DEBUG + bool + default y + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + serial number. This feature requires a signed whitelist image + and bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file path" + depends on HAVE_PSP_WHITELIST_FILE + +config HAVE_SPL_FILE + bool + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin" + +config PSP_SOFTFUSE_BITS + string "PSP Soft Fuse bits to enable" + default "" + help + Space separated list of Soft Fuse bits to enable. + Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) + Bit 7: Disable PSP postcodes on Renoir and newer chips only + (Set by PSP_DISABLE_PORT80) + Bit 15: PSP debug output destination: + 0=SoC MMIO UART, 1=IO port 0x3F8 + + See #57299 (NDA) for additional bit definitions. +endmenu + + +endif # SOC_AMD_GENOA diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 7523b68..de996d6 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -14,4 +14,124 @@ CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 endif +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Implementation +# Guide for Server EPYC Processors" #57299 +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +ifeq ($(CONFIG_HAVE_SPL_FILE),y) +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \ + $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + --use-pspsecureos \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize 0x1000000 + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + endif diff --git a/src/soc/amd/genoa/fw.cfg b/src/soc/amd/genoa/fw.cfg new file mode 100644 index 0000000..d8297fd --- /dev/null +++ b/src/soc/amd/genoa/fw.cfg @@ -0,0 +1,54 @@ +# PSP fw config file +FIRMWARE_LOCATION 3rdparty/amd_blobs/genoa/PSP +SOC_NAME Genoa + +# type file +# PSP +AMD_PUBKEY_FILE Typex0_0_0_0_AmdPubKey.bin +PSPBTLDR_FILE Typex1_0_0_0_PspBootLoader.bin Lbb +PSPRCVR_FILE Typex3_0_0_0_PspRecBL.bin +PSP_SMUFW1_SUB0_FILE Typex8_0_0_0_Smu.bin +PSP_SMUFW1_SUB1_FILE Typex8_0_0_1_Smu.bin +PSP_SMUFW1_SUB2_FILE Typex8_0_0_2_Smu.bin +PSPSECUREDEBUG_FILE Typex9_0_0_0_DbgKey.bin +PSP_OEM_ABL_KEY_FILE Typexa_0_0_0_OemAblKey.bin +PSP_SMUFW2_SUB0_FILE Typex12_0_0_0_Smu2.bin +PSP_SMUFW2_SUB1_FILE Typex12_0_0_1_Smu2.bin +PSP_SMUFW2_SUB2_FILE Typex12_0_0_2_Smu2.bin Lbb +PSP_SEC_DEBUG_FILE Typex13_0_0_0_PspEarlyUnlock.bin Lbb +PSP_IKEK_FILE Typex21_0_0_0_ikek.bin +PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin +PSP_SECG0_FILE Typex24_0_0_0_SecureGasket.bin +PSP_SECG1_FILE Typex24_0_0_1_SecureGasket.bin +PSP_SECG2_FILE Typex24_0_0_2_SecureGasket.bin +PSP_MP5FW_SUB0_FILE Typex2a_0_0_0_Mp5Fw.bin +PSP_MP5FW_SUB1_FILE Typex2a_0_0_1_Mp5Fw.bin +PSP_MP5FW_SUB2_FILE Typex2a_0_0_2_Mp5Fw.bin +PSP_ABL0_FILE Typex30_0_0_0_PspAgesaBL0.bin +SEV_CODE_FILE Typex39_0_0_0_SevCode.bin +SEV_DATA_FILE Typex38_0_0_0_SevData.bin +PSP_DXIOFW_FILE Typex42_0_0_0_DxioFw.bin +UNIFIEDUSB_FILE Typex44_0_0_0_UsbPhyFw.bin +DRTMTA_FILE Typex47_0_0_0_DrtmTa.bin +KEYDBBL_FILE Typex50_0_0_0_PspBlPubKey.bin +SPL_TABLE_FILE Typex55_0_0_0_BLAntiRB.bin Lbb +PSP_MPIOFW_FILE Typex5d_0_0_0_MPIOOffchipFW.bin +PSP_RIB_FILE_SUB0 Typex76_0_0_0_RIB.bin +PSP_MPDMATFFW_FILE Typex8c_0_0_0_MpdmaTfFw.bin +PSP_GMI3PHYFW_FILE Typex91_0_0_0_Gmi3PhyFw.bin +PSP_MPDMAPMFW_FILE Typex92_0_0_0_MpdmaPmFw.bin +AMD_FUSE_CHAIN Dummy Lbb + +# BDT +PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin +PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin +# TODO: Typex69_0_0_0_EarlyVgaImage.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/76498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Gerrit-Change-Number: 76498 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/cse: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Paul Menzel, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577?usp=email ) Change subject: soc/intel/cse: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 52: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/f8edc44b_83a91f24 : PS52, Line 1115: if (backup_psr_resp.status != PSR_STATUS_SUCCESS) > thinking loud here, won't we run into this case while sending PSR backup for non-vpro sku ? […] if we have this check for PSR bit (https://review.coreboot.org/c/coreboot/+/74874) we will not be invoking this on non VPRO skus -- To view, visit https://review.coreboot.org/c/coreboot/+/74577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 52 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 15:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Krishna P Bhat D, Rizwan Qureshi, Subrata Banik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74874/comment/a83d5fc8_b46397d4 : PS6, Line 1077: printk(BIOS_INFO, "Check if PSR is supported in this SKU !\n"); > same Acknowledged https://review.coreboot.org/c/coreboot/+/74874/comment/d032ccf6_95424943 : PS6, Line 1090: printk(BIOS_DEBUG, "PSR is supported in this SKU !\n"); > we don't need such prints Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 7 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 14:50:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Krishna P Bhat D, Rizwan Qureshi, Subrata Banik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74874/comment/b1eef0e2_6c4844f2 : PS6, Line 1106: > shouldn't we check this at line #1100 ? […] the command needs to be run after CSE is in RW .. so called it after we switch to RW. This is being called in the case when we do a CSE downgrade. Will not be invoked in regular boot flow . so should not have boot time impact -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 14:48:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: payloads/edk2: Move TPM disable to separate Kconfig
by Sean Rhodes (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78031?usp=email ) Change subject: payloads/edk2: Move TPM disable to separate Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01509fea2dd42b741c00abcf9fb8b936e895b932 Gerrit-Change-Number: 78031 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 14:47:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, Tarun. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78054?usp=email ) Change subject: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/78054/comment/3ed581ae_fa1c6a73 : PS3, Line 442: # The default offset to store CSE RW FW version information is at 68. In Intel Meteor Lake based : # systems that use PSR, the additional size required to keep CSE RW FW version information and : # PSR back-up status in adjacent CMOS memory at offset 68 is not available. Offset 161 has : # enough space to keep both the CSE related information together. Hence override the default : # offset to 161. > ``` […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78054?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Gerrit-Change-Number: 78054 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 14:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2023