coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3824 discussions

[XS] Change in coreboot[main]: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake
by Rizwan Qureshi (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Eran Mitrani, Hannah Williams, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Subrata Banik, Tarun, Tarun Tuli, sridhar siricilla. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76115?usp=email ) Change subject: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake ...................................................................... Patch Set 14: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/76115/comment/3b3765cc_1a1fb0cb : PS11, Line 29: select SOC_INTEL_CSE_LITE_PSR > > agreed . […] we have created a cros-bug https://partnerissuetracker.corp.google.com/issues/302285864 and have a thread with CSE team internally. -- To view, visit https://review.coreboot.org/c/coreboot/+/76115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39af029a5f0c018a5db3ac68191764abfa9518ac Gerrit-Change-Number: 76115 Gerrit-PatchSet: 14 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:48:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/picasso: add eMMC MMIO device to devicetree
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77990?usp=email ) Change subject: soc/amd/picasso: add eMMC MMIO device to devicetree ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > yep, this commenting out does allow me to get as far as I had previously gotten. […] hm, this is unexpected. i'm not sure if the aoac registers direct;y control the hardware or if it makes some firmware on some of the embedded microprocessors do something. if the latter is the case, this might be due to using unsupported psp/smu/... binaries or it might be a mobile vs desktop thing. at least i verified that this patch didn't break things on mobile picasso when using the binaries from amb_blobs -- To view, visit https://review.coreboot.org/c/coreboot/+/77990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5453b69df776d2ce1f3be11e37cd26c8c64f0cd5 Gerrit-Change-Number: 77990 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:47:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Marty E. Plummer <hanetzer(a)startmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/cse: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Paul Menzel, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577?usp=email ) Change subject: soc/intel/cse: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 54: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/d3d8fb7b_dfc335d1 : PS52, Line 1152: CONFIG(SOC_INTEL_CSE_LITE_PSR) > use this as the first case […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/74577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 54 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:41:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/cse: Add function to get cse_bp_info early
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Krishna P Bhat D, Rizwan Qureshi, Subrata Banik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78053?usp=email ) Change subject: soc/intel/cse: Add function to get cse_bp_info early ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/78053/comment/9100382d_fe1aa2f2 : PS2, Line 424: store_cse_bp_info_in_cbmem > > store_cse_bp_info_in_cbmem() is being called by https://review.coreboot. […] as suggested we added a function sync_cse_bp_info_to_cbmem which add cbmem entry if not present and retrieves the entry https://review.coreboot.org/c/coreboot/+/78053/comment/9588a878_f4d8b12d : PS2, Line 469: cbmem_find(CBMEM_ID_CSE_BP_INFO) > cbmem_find(CBMEM_ID_CSE_BP_INFO) is used only in this case, so better not to move it to common funct […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Gerrit-Change-Number: 78053 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:37:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/common: use common physical address bit reservation code
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jérémy Compostella, Marshall Dawson, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email ) Change subject: soc/amd/common: use common physical address bit reservation code ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/cpu/noncar/cpu.c: https://review.coreboot.org/c/coreboot/+/78074/comment/b001105f_a620e12c : PS2, Line 45: else > oh, i like that one. will add that as a follow up and add a suggested-by tag. […] pushed CB:78176 that implements 1. i didn't include 2 and 3, since i didn't find a good name for the temporary variable and kept the parenthesis, since i find that a bit easier to read. but i agree that that is mainly personal preference -- To view, visit https://review.coreboot.org/c/coreboot/+/78074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Gerrit-Change-Number: 78074 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:35:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78176?usp=email ) Change subject: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits ...................................................................... soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits Simplify the code a bit by returning 0 early in the function when the SYSCFG_MSR_SMEE bit isn't set. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 --- M src/soc/amd/common/block/cpu/noncar/cpu.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/78176/1 diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index eefd62f..136cb42 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -38,10 +38,9 @@ /* Number of most significant physical address bits reserved for secure memory encryption */ unsigned int get_reserved_phys_addr_bits(void) { - if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE) - return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & - CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >> - CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT; - else + if (!(rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)) return 0; + + return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >> + CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT; } -- To view, visit https://review.coreboot.org/c/coreboot/+/78176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 Gerrit-Change-Number: 78176 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... Patch Set 8: (4 comments) File src/soc/intel/common/block/cse/cse_lite_cmos.c: https://review.coreboot.org/c/coreboot/+/77069/comment/b929552c_4c713e6f : PS7, Line 113: int8_t > int ? kept it int8_t as value is either 1 or 0 File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/b6e900ba_2b829ed4 : PS7, Line 176: backup_status > nit: status or value […] Acknowledged https://review.coreboot.org/c/coreboot/+/77069/comment/b06ef769_c704bd5d : PS7, Line 176: int8_t > int int8_t as the value if either 0 or 1 File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/a2c1ac65_8231004a : PS5, Line 171: 0x55 > > Hi Subrata , We kept the values 0x55 and 0x22 to make sure these are not commonly occuring values […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, sridhar siricilla. Anil Kumar K has uploaded a new patch set (#8) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Anil Kumar K, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... soc/intel/cse: Implement APIs to access PSR backup status in CMOS PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data. Since firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. So adding a CMOS variable for the same. This patch implements API to access PSR backup status stored in CMOS. The get API allows to retrieve the PSR backup status from CMOS memory. The update API allows to update the PSR backup status in CMOS. BRANCH=None BUG=b:273207144 TEST=Able to retrieve PSR backup status across resets. Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite_cmos.c M src/soc/intel/common/block/cse/cse_lite_cmos.h M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/77069/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, Tarun. Anil Kumar K has uploaded a new patch set (#5) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/78054?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET ...................................................................... soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET CSE firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. In the subsequent patches, a CMOS structure to store PSR back-up status will be added. The current SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET of 68 can only store cse_specific_info, as ramtop is at offset 100 and PSR back-up status structure will not be able to fit within the range. This patch overrides the SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET to 161 to accommodate all CSE related info in adjacent CMOS memory. BUG=b:273207144 TEST=Verify CSE RW FW versions are stored in CMOS memory in rex. Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/78054/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78054?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Gerrit-Change-Number: 78054 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/intel/cse: Add function to get cse_bp_info early
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi. Anil Kumar K has uploaded a new patch set (#4) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/78053?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Anil Kumar K, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cse: Add function to get cse_bp_info early ...................................................................... soc/intel/cse: Add function to get cse_bp_info early PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. Sending cse_get_bp_info command in ramstage takes additional boot time of ~45-55ms on rex. To avoid the boot time penalty, this patch provides an API to get the cse_bp_info in early romstage. The response data is then migrated to cbmem once memory is initialized. The same data in cbmem can be utilized in ramstage to perform other cse_fw_sync actions. This patch also adds check to validate cse_bp_info in cbmem and avoids sending the command again if the data is valid. BUG=b:273207144 TEST=Verify the command works in early romstage, data is migrated to cbmem and valid data is available in ramstage on rex. Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/78053/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Gerrit-Change-Number: 78053 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023