coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Jérémy Compostella (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Lance Zhao, Subrata Banik, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 5: (2 comments) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/78164/comment/83d029d8_a4225d52 : PS5, Line 95: You don't need add an extra line. https://review.coreboot.org/c/coreboot/+/78164/comment/b6249324_2207fe2d : PS5, Line 99: Selected by platforms that slp_s0 freq is varies in different Intel SoC Where is the definition of CONFIG_SOC_INTEL_SLP_S0_FREQ ? Why isn't it prefixed with ACPI. It is different than what we discussed earlier today. -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 5 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits
by Jérémy Compostella (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78176?usp=email ) Change subject: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 Gerrit-Change-Number: 78176 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:45:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cse: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Paul Menzel, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577?usp=email ) Change subject: soc/intel/cse: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 54: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/015e1d4c_6935d232 : PS50, Line 1125: An attempt to send PSR back-up command has been made. > Sure, I have added section in the document in end as "Opens from code review for retrospective" Subrata, Rizwan . based on this discussion are we good w.r.t to this patch merge or is there any other opens to be taken care ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 54 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:38:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jakub Czapiga, Subrata Banik, Sukumar Ghorai. Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78177?usp=email to look at the new patch set (#4). Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ...................................................................... soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel® 64 and IA-32 Architectures Software Developer’s Manual MSR 0x632: PC10 residency counter is at same frequency as the TSC. BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/soc/intel/common/block/acpi/lpit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jakub Czapiga, Subrata Banik, Sukumar Ghorai. Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78177?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ...................................................................... soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel® 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/soc/intel/common/block/acpi/lpit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 3 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/cse: Add function to get cse_bp_info early
by Anil Kumar K (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Krishna P Bhat D, Rizwan Qureshi, Subrata Banik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78053?usp=email ) Change subject: soc/intel/cse: Add function to get cse_bp_info early ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/78053/comment/a92129be_ac9f2581 : PS2, Line 507: if (cbmem_online()) : store_cse_bp_info_in_cbmem(); > > We have to consider the case of cse_fw_sync() being called in late romstage also like in JSL, TGL. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Gerrit-Change-Number: 78053 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:14:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake
by Subrata Banik (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Eran Mitrani, Hannah Williams, Jakub Czapiga, Kapil Porwal, Krishna P Bhat D, Rizwan Qureshi, Tarun, Tarun Tuli, sridhar siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76115?usp=email ) Change subject: soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for Meteorlake ...................................................................... Patch Set 14: Code-Review+2 (2 comments) Patchset: PS12: > pls check cl:74874 Acknowledged File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/76115/comment/8cdb8ba3_5c262295 : PS11, Line 29: select SOC_INTEL_CSE_LITE_PSR > we have created a cros-bug https://partnerissuetracker.corp.google. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/76115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39af029a5f0c018a5db3ac68191764abfa9518ac Gerrit-Change-Number: 76115 Gerrit-PatchSet: 14 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:12:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email ) Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ...................................................................... soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel® 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/soc/intel/common/block/acpi/lpit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/1 diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 38a402f..3d22f4a 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -31,7 +31,7 @@ pkg_counter->residency_counter.bit_width = 64; pkg_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_FIXED; pkg_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - pkg_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + pkg_counter->counter_frequency = 0; /* same freq as TSC */ /* Min. residency and worst-case latency (from FSP and vendor dumps) */ pkg_counter->min_residency = 30000; /* break-even: 30 ms */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Subrata Banik, Sukumar Ghorai, Tarun. Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78164?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... soc/intel: Fix slp-s0 residency counter frequency LPIT table Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf System sleep time (SLP_S0 signal asserted) is measured in ticks, for MTL in 122μs granularity/ticks. BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency after s0ix cycle cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/acpi/Kconfig M src/include/acpi/acpi.h M src/soc/intel/meteorlake/Kconfig 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 5 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/cse: Back up PSR data during CSE FW downgrade
by Rizwan Qureshi (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Paul Menzel, Subrata Banik, sridhar siricilla. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577?usp=email ) Change subject: soc/intel/cse: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 54: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/b87e3897_2e168bfd : PS50, Line 1125: An attempt to send PSR back-up command has been made. > > > something like "Back-up failed", is what i'm looking for record purposes. […] Sure, I have added section in the document in end as "Opens from code review for retrospective" -- To view, visit https://review.coreboot.org/c/coreboot/+/74577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 54 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 18:55:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2023