coreboot-gerrit September 2023

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[XS] Change in coreboot[main]: include/acpi/acpi_pld.h: Remove comment on PLD
by Martin L Roth (Code Review) 28 Sep '23

28 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70297?usp=email ) Change subject: include/acpi/acpi_pld.h: Remove comment on PLD ...................................................................... include/acpi/acpi_pld.h: Remove comment on PLD Remove comment on PLD horizontal position as ACPI spec 6.5 define that field: https://uefi.org/specs/ACPI/6.5/06_Device_Configuration.html?highlight=pld%… Change-Id: I228e0780699c223f1e3227fd45ec094e0c46205e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/include/acpi/acpi_pld.h 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h index f89a680..98d7f9e 100644 --- a/src/include/acpi/acpi_pld.h +++ b/src/include/acpi/acpi_pld.h @@ -22,12 +22,6 @@ PLD_VERTICAL_POSITION_LOWER }; -/* - * The ACPI spec 6.2A does not define the horizontal position field. - * These values are taken from the IASL compiler: - * https://github.com/acpica/acpica/blob/master/source/components/utilities/ut… - */ - enum acpi_pld_horizontal_position { PLD_HORIZONTAL_POSITION_LEFT, PLD_HORIZONTAL_POSITION_CENTER, -- To view, visit https://review.coreboot.org/c/coreboot/+/70297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I228e0780699c223f1e3227fd45ec094e0c46205e Gerrit-Change-Number: 70297 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: checkpatch.conf: Remove non-existent warnings
by Martin L Roth (Code Review) 28 Sep '23

28 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77773?usp=email ) Change subject: checkpatch.conf: Remove non-existent warnings ...................................................................... checkpatch.conf: Remove non-existent warnings Change-Id: I05ed882990c45625ad5f08a2bff21a7fda2055db Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77773 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M .checkpatch.conf 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/.checkpatch.conf b/.checkpatch.conf index 8c6265c..ac261a4 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -8,9 +8,6 @@ --ignore INITIALISED_STATIC --ignore LINE_SPACING --ignore NEW_TYPEDEFS ---ignore PREFER_ALIGNED ---ignore PREFER_PACKED ---ignore PREFER_PRINTF --ignore SPLIT_STRING --ignore BLOCK_COMMENT_STYLE --ignore AVOID_EXTERNS -- To view, visit https://review.coreboot.org/c/coreboot/+/77773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05ed882990c45625ad5f08a2bff21a7fda2055db Gerrit-Change-Number: 77773 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd: rework SPL file override and SPL fusing handling
by Felix Held (Code Review) 28 Sep '23

28 Sep '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78178?usp=email ) Change subject: soc/amd: rework SPL file override and SPL fusing handling ...................................................................... soc/amd: rework SPL file override and SPL fusing handling The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. This happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/skyrim/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 13 files changed, 88 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/78178/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7f233be..30d9277 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -106,13 +106,12 @@ string default "src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg" -config HAVE_SPL_FILE +config PERFORM_SPL_FUSING bool default y config SPL_TABLE_FILE string - depends on HAVE_SPL_FILE default "3rdparty/blobs/mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin" if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 4e9ae98..3adbda4 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -96,13 +96,12 @@ depends on CHROMEOS default y -config HAVE_SPL_FILE +config PERFORM_SPL_FUSING bool default y config SPL_TABLE_FILE string - depends on HAVE_SPL_FILE default "3rdparty/blobs/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin" config HAVE_SPL_RW_AB_FILE @@ -111,7 +110,6 @@ config SPL_RW_AB_TABLE_FILE string - depends on HAVE_SPL_RW_AB_FILE default "3rdparty/blobs/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME.sbin" config SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 160bc65..ba90633 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -376,19 +376,27 @@ depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific SPL table file, which is created by AMD - and put to 3rdparty/blobs. + Send the Security Patch Level (SPL) fusing command to the PSP so that + it is made sure that the minimal SPL version is written to the SoC's + fuse bits so that the embedded firmwares can't be rolled back to a + version with lower SPL. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 76cb9e8..c92bb0d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -91,9 +91,7 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 0f15963..a89d4e9 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -29,6 +29,6 @@ smm-y += psp_gen2.c smm-y += psp_smm_gen2.c -ramstage-$(CONFIG_HAVE_SPL_FILE) += spl_fuse.c +ramstage-$(CONFIG_PERFORM_SPL_FUSING) += spl_fuse.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index c4f8a9d..417912e 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -117,13 +117,27 @@ string "Debug whitelist file path" depends on HAVE_PSP_WHITELIST_FILE -config HAVE_SPL_FILE - bool +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" + default n + help + Send the Security Patch Level (SPL) fusing command to the PSP so that + it is made sure that the minimal SPL version is written to the SoC's + fuse bits so that the embedded firmwares can't be rolled back to a + version with lower SPL. + + If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index efbd3b1..6b936b6 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -46,9 +46,7 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index ae4b190..0807909 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -349,37 +349,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/glinda/PSP/wtl-mrg.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP so that + it is made sure that the minimal SPL version is written to the SoC's + fuse bits so that the embedded firmwares can't be rolled back to a + version with lower SPL. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 25b2fe4..ea2a48b 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -86,14 +86,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d179f35..abfe52a 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -406,37 +406,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/mendocino/PSP/wtl-mdn.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP so that + it is made sure that the minimal SPL version is written to the SoC's + fuse bits so that the embedded firmwares can't be rolled back to a + version with lower SPL. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 14eb363..9442083 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -89,14 +89,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 18ed58f..365fd1f 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -361,37 +361,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP so that + it is made sure that the minimal SPL version is written to the SoC's + fuse bits so that the embedded firmwares can't be rolled back to a + version with lower SPL. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index b2f566d..d589bf1 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -92,14 +92,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool -- To view, visit https://review.coreboot.org/c/coreboot/+/78178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Gerrit-Change-Number: 78178 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/pc80/pc: Split up PS/2 keyboard/mouse ACPI definitions
by Matt DeVillier (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jonathon Hall, Paul Menzel, Tim Wawrzynczak, ron minnich. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78096?usp=email ) Change subject: drivers/pc80/pc: Split up PS/2 keyboard/mouse ACPI definitions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13a4c2caf8dc9e5004b775dc0a9ac2488e39f184 Gerrit-Change-Number: 78096 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 20:24:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: Make C1e configurable
by Matt DeVillier (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Jeremy Soller, Martin L Roth, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun Tuli, Tim Crawford. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77088?usp=email ) Change subject: soc/intel/alderlake: Make C1e configurable ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/77088/comment/18e48874_933c093f : PS5, Line 1071: s_cfg->C1e = !config->disable_c1e; since the original code was to disable based on CPUID, and boards can use CPUs having multiple CPUIDs, I think the best way to maintain current behavior for existing boards is to make this an enum rather than a bool, and have options {CPUID=0, ENABLED, DISABLED) so that not setting the register will maintain existing behavior, but boards/variants are free to override. -- To view, visit https://review.coreboot.org/c/coreboot/+/77088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Gerrit-Change-Number: 77088 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 28 Sep 2023 20:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78164?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... soc/intel: Fix slp-s0 residency counter frequency LPIT table Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf System sleep time (SLP_S0 signal asserted) is measured in ticks, for MTL in 122μs granularity/ticks. BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency after s0ix cycle cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/acpi/Kconfig M src/include/acpi/acpi.h M src/soc/intel/meteorlake/Kconfig 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 6 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 5: (3 comments) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/78164/comment/e0b6ad32_fff037a2 : PS5, Line 95: > You don't need add an extra line. Acknowledged https://review.coreboot.org/c/coreboot/+/78164/comment/74e78b73_747cab24 : PS5, Line 99: Selected by platforms that slp_s0 freq is varies in different Intel SoC > Where is the definition of CONFIG_SOC_INTEL_SLP_S0_FREQ ? Why isn't it prefixed with ACPI. […] Acknowledged File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/f8df4e84_31b59a9d : PS4, Line 456: _TSC > `TSC` is one of the option (0 means TSC), right? yes, refer https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_…, section 2.2.1: value of 0 indicates that counter runs at TSC frequency -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 5 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Sep 2023 20:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/common: use common physical address bit reservation code
by Jérémy Compostella (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email ) Change subject: soc/amd/common: use common physical address bit reservation code ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/78074/comment/1ba8c132_db8d07e8 : PS2, Line 1: SOC_AMD_COMMON_BLOCK_CAR I am curious: why don't you also select it for `SOC_AMD_COMMON_BLOCK_CAR` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/78074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Gerrit-Change-Number: 78074 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: */include/cpu: use unsigned int for number of address bits
by Jérémy Compostella (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Felix Held, Marshall Dawson. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78072?usp=email ) Change subject: */include/cpu: use unsigned int for number of address bits ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I know it won't change a lot but shouldn't be using size_t to handle a size ? -- To view, visit https://review.coreboot.org/c/coreboot/+/78072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e67db6bf0c38f743b50e7273449cc028de13a8c Gerrit-Change-Number: 78072 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:56:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
by Jérémy Compostella (Code Review) 28 Sep '23

28 Sep '23

Attention is currently required from: Felix Held, Marshall Dawson. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78073?usp=email ) Change subject: arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0059e63a160e60ddee280635bba72d363deca7f7 Gerrit-Change-Number: 78073 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 28 Sep 2023 19:54:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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