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Change subject: soc/amd/common: use common physical address bit reservation code
......................................................................
soc/amd/common: use common physical address bit reservation code
Instead of having the get_usable_physical_address_bits function that
only got used in the data fabric domain resource reporting code, drop
this function, select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT in the
common AMD non-CAR CPU and rename get_sme_reserved_address_bits to
get_reserved_phys_addr_bits so that the common cpu_phys_address_size
function will return the correct number of usable physical address bits
which now can be used everywhere. The common AMD CAR CPU support is only
selected by Stoneyridge which doesn't support secure memory encryption,
so RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT isn't selected by the
SOC_AMD_COMMON_BLOCK_CAR Kconfig option.
Before only the MMIO region reporting took the reserved physical address
bits into account, but now also the MTRR calculation will take those
reserved bits into account. See the AMD64 Programmers Manual volume 2
(document number 24593) for details. Chapter 7.10.5 from revision 3.41
of this document was used as a reference. The MTRR handling code in
older Linux kernels complains when the upper reserved bits in the MTRR
mask weren't set, but sets them after complaining and then continues to
boot. This issue is no longer present in version version 6.5 of the
Linux kernel.
The calculation of the TSEG mask however still needs to take all
physical bits into account, including the ones reserved for the memory
encryption. When not setting the reserved bits in the TSEG mask, the
Mandolin board with a Picasso APU won't boot to the OS any more due to
not returning from SeaBIOS calling into the VBIOS. Haven't root-caused
what exactly causes this breakage, but I think previously when something
else was wrong with the SMM initialization, also something went wrong
when calling into the VBIOS.
TEST=Ubuntu 2023.10 nightly build boots on Mandolin via SeaBIOS and EDK2
and Windows 10 boots on it via EDK2.
TEST=On Ubuntu 2022.04 LTS, the kernel complained with the following
warning, but it still continues the boot process as described above:
mtrr: your BIOS has configured an incorrect mask, fixing it.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e
---
M src/soc/amd/common/block/cpu/Kconfig
M src/soc/amd/common/block/cpu/noncar/Makefile.inc
M src/soc/amd/common/block/cpu/noncar/cpu.c
M src/soc/amd/common/block/cpu/smm/smm_relocate.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/include/amdblocks/cpu.h
6 files changed, 12 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78074/3
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Change subject: arch/riscv/romstage: Start from assembly
......................................................................
Patch Set 1: -Code-Review
(1 comment)
Patchset:
PS1:
That wasn't the button I was looking for.
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Change subject: */include/cpu: use unsigned int for number of address bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I know it won't change a lot but shouldn't be using size_t to handle a size ?
hmm, good question. since i expect that values to be at most 64, i don't think that this would make any difference in practice
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Change subject: arch/riscv/romstage: Start from assembly
......................................................................
Patch Set 1: Code-Review+2
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Change subject: arch/x86/riscv: Use 'all' target to include files in all stages
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/asrock/b75m-itx: Order Kconfig selects alphabetically
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/guybrush: Disable WLAN ASPM
......................................................................
Patch Set 6: Code-Review+2
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Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table
......................................................................
soc/intel: Fix slp-s0 residency counter frequency LPIT table
Intel platforms use Low Power Idle Table(LPIT) to enumerate platform
Low Power Idle states. There are two types of low power residencies
a) CPU PKG C10 - read via MSR (Function fixed hardware interface)
b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped
Ref. https://www.uefi.org/sites/default/files/resources/
Intel_ACPI_Low_Power_S0_Idle.pdf
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
MTL in 122μs granularity/ticks.
BUG=b:300440936
TEST=check kernel cpuidle sysfs for sleep residency after s0ix cycle
cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/acpi/Kconfig
M src/include/acpi/acpi.h
M src/soc/intel/meteorlake/Kconfig
3 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/7
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Change subject: soc/amd/common: use common physical address bit reservation code
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/78074/comment/70ffb7aa_4d97c932 :
PS2, Line 1: SOC_AMD_COMMON_BLOCK_CAR
> I am curious: why don't you also select it for `SOC_AMD_COMMON_BLOCK_CAR` ?
only stoneyridge uses the legacy SOC_AMD_COMMON_BLOCK_CAR and stoneyridge doesn't support secure memory encryption
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