coreboot-gerrit September 2023

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[XS] Change in coreboot[main]: soc/intel: separate slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jakub Czapiga, Paul Menzel, Subrata Banik. Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78177?usp=email to look at the new patch set (#6). Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table ...................................................................... soc/intel: separate slp-s0 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_…, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Where as slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/lpit.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 6 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 8: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/f43d0733_9bedf656 : PS7, Line 456: #if CONFIG(ACPI_SOC_INTEL_SLP_S0_FREQ_VALUE) > nit: […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 8 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 07:08:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: seperate slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jakub Czapiga, Paul Menzel, Subrata Banik. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email ) Change subject: soc/intel: seperate slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78177/comment/aea0bb72_022595ec : PS4, Line 9: Table(LPIT) > Please add a space before the (. Acknowledged https://review.coreboot.org/c/coreboot/+/78177/comment/7afedd8a_7945e523 : PS4, Line 12: read via memory mapped > … IO? Acknowledged https://review.coreboot.org/c/coreboot/+/78177/comment/b08602b9_9fae5ad6 : PS4, Line 14: https://www.uefi.org/sites/default/files/resources/ : Intel_ACPI_Low_Power_S0_Idle.pdf > The URL should be one line. Acknowledged https://review.coreboot.org/c/coreboot/+/78177/comment/0b91e1ba_970f2b79 : PS4, Line 23: cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us > What device? What do you check exactly? Before your patch it was 0? Acknowledged File src/soc/intel/common/block/acpi/lpit.c: https://review.coreboot.org/c/coreboot/+/78177/comment/f14c1786_59c80eb4 : PS4, Line 34: pkg_counter->counter_frequency = 0; /* same freq as TSC */ > The macro is defined as 0. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 29 Sep 2023 07:08:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78164?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... soc/intel: Fix slp-s0 residency counter frequency LPIT table Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf System sleep time (SLP_S0 signal asserted) is measured in ticks, for meteorlake soc in 122us granularity/ticks. BUG=b:300440936 TEST=check kernel cpuidle sysfs for non-zero residency after s0ix cycle cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/include/acpi/acpi.h M src/soc/intel/meteorlake/Kconfig 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 8 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel: seperate slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jakub Czapiga, Subrata Banik, Sukumar Ghorai. Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78177?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel: seperate slp-s0 residency counter frequency in LPIT table ...................................................................... soc/intel: seperate slp-s0 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_…, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Where as slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/lpit.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 5 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/siemens: Move selects from Kconfig.name to Kconfig
by Mario Scheithauer (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Felix Singer. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75078?usp=email ) Change subject: mb/siemens: Move selects from Kconfig.name to Kconfig ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/mainboard/siemens/mc_apl1/Kconfig: https://review.coreboot.org/c/coreboot/+/75078/comment/d579ae42_b3b8f3f7 : PS5, Line 10: config BOARD_SIEMENS_MC_APL1 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL2 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL3 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL4 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL5 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL6 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 : : config BOARD_SIEMENS_MC_APL7 : select BOARD_SIEMENS_BASEBOARD_MC_APL1 > Isn't it then perhaps better to select _BASEBOARD_ in variant/.. […] We can also move this later on variant level, or leave it here. -- To view, visit https://review.coreboot.org/c/coreboot/+/75078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2 Gerrit-Change-Number: 75078 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 29 Sep 2023 06:51:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
by Paul Menzel (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jakub Czapiga, Sukumar Ghorai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78177/comment/d47cb9ac_c739db2e : PS4, Line 9: Table(LPIT) Please add a space before the (. https://review.coreboot.org/c/coreboot/+/78177/comment/614061ff_02249cad : PS4, Line 12: read via memory mapped … IO? https://review.coreboot.org/c/coreboot/+/78177/comment/19c1335b_6501ebc3 : PS4, Line 14: https://www.uefi.org/sites/default/files/resources/ : Intel_ACPI_Low_Power_S0_Idle.pdf The URL should be one line. https://review.coreboot.org/c/coreboot/+/78177/comment/5f6a68b0_490563fd : PS4, Line 23: cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us What device? What do you check exactly? Before your patch it was 0? File src/soc/intel/common/block/acpi/lpit.c: https://review.coreboot.org/c/coreboot/+/78177/comment/c3781ec7_363fe4d2 : PS4, Line 34: pkg_counter->counter_frequency = 0; /* same freq as TSC */ The macro is defined as 0. src/include/acpi/acpi.h:#define ACPI_LPIT_CTR_FREQ_TSC 0 What is the difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 05:30:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Subrata Banik (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 7: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/79ad541d_73b7d42a : PS7, Line 456: #if CONFIG(ACPI_SOC_INTEL_SLP_S0_FREQ_VALUE) nit: ``` #if CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_VALUE != 0 #define ACPI_LPIT_CTR_FREQ_TSC CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ #else #define ACPI_LPIT_CTR_FREQ_TSC 0 #endif ``` or just replace ACPI_LPIT_CTR_FREQ_TSC macro in the code (sys_counter->counter_frequency) with CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ directly then you don't need this preprocessoring -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 7 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 05:25:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
by Subrata Banik (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jakub Czapiga, Sukumar Ghorai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email ) Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Gerrit-Change-Number: 78177 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 05:20:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table
by Sukumar Ghorai (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ...................................................................... Patch Set 7: (2 comments) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/78164/comment/332287d3_0edbb879 : PS7, Line 95: config ACPI_SOC_INTEL_SLP_S0_FREQ_VALUE : bool : help : Selected by platforms that slp_s0 freq is varies in different Intel SoC : > can we use below config instead - […] src/include/acpi/acpi.h: #if CONFIG(ACPI_SOC_INTEL_SLP_S0_FREQ) does not work as following statement also in src/soc/intel/meteorlake/Kconfig:443:config ACPI_SOC_INTEL_SLP_S0_FREQ config ACPI_SOC_INTEL_SLP_S0_FREQ Need advice how to overwrite the ACPI_SOC_INTEL_SLP_S0_FREQ from src/soc/intel/meteorlake/Kconfig File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/5be2204b_eb9a1e1a : PS4, Line 456: _TSC > In that case, also rename the macro from `ACPI_LPIT_CTR_FREQ_TSC` to `ACPI_LPIT_CTR_FREQ`. ok. will submit as separate patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 7 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 05:18:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2023