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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email )
Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command
......................................................................
Patch Set 7:
(4 comments)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/88a8beb9_797d75da :
PS6, Line 1106:
> the command needs to be run after CSE is in RW .. so called it after we switch to RW.
Ack kindly write that in comment section of the helper function, this API is only supported w/ CSE is RW.
> This is being called in the case when we do a CSE downgrade. Will not be invoked in regular boot flow . so should not have boot time impact
that is okay but at worst case, we should know for sure the boot time impact. I'm afraid that, the CSE is taking longer time without any reason.
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/2d89070e_90a70db1 :
PS7, Line 1078: first check if PSR is supported by the SKU
nit:
```
Check if SoC has support for PSR feature (typically PSR feature is only supported by vpro SKU)
```
https://review.coreboot.org/c/coreboot/+/74874/comment/640171e5_87153130 :
PS7, Line 1086: /* PSR is not supported in this SKU */
you don't need this comment
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74874/comment/1d499222_fbf2f3d0 :
PS7, Line 43: #define ME_FW_FEATURE_PSR BIT(5)
align with line 42 (need two space may be ?)
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Hello Bora Guvendik, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Li1 Feng, Subrata Banik, Tarun,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78179?usp=email
to look at the new patch set (#2).
Change subject: mb/google/rex: Fix ISH I2C pad for suspend
......................................................................
mb/google/rex: Fix ISH I2C pad for suspend
During suspend, the ISH I2C transactions cannot go through
Because the GPIO pads remain the pervious value.
The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus
active and functional during suspend.
BUG=302612549
TEST=on Google/rex platform with ISH enabled, do suspend_stress_test
and check that no i2c failure.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/78179/2
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Change subject: soc/intel/cse: Add function to get cse_bp_info early
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
I will start the validation as this CL now looks good.
kindly don't merge the CL unless i get back with the data
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Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table
......................................................................
Patch Set 7: Code-Review+2
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Change subject: soc/amd/picasso: add eMMC MMIO device to devicetree
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> hm, this is unexpected. […]
just for the record, I told you on libera but for any readers: I'm not using any blobs from the vendor as of this moment.
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Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78179?usp=email )
Change subject: mb/google/rex: Fix ISH I2C pad for suspend
......................................................................
mb/google/rex: Fix ISH I2C pad for suspend
During suspend, the ISH I2C transactions cannot go through
Because the GPIO pads remain the pervious value.
The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus
active and functional during suspend.
BUG=302612549
TEST=on Rex platform with ISH enabled, do suspend_stress_test and
check that no i2c failure.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/78179/1
diff --git a/src/mainboard/google/rex/variants/rex0/fw_config.c b/src/mainboard/google/rex/variants/rex0/fw_config.c
index 86cb781..cea55ec 100644
--- a/src/mainboard/google/rex/variants/rex0/fw_config.c
+++ b/src/mainboard/google/rex/variants/rex0/fw_config.c
@@ -85,9 +85,9 @@
static const struct pad_config ish_enable_pads[] = {
/* GPP_B02 : ISH I2C0_SDA */
- PAD_CFG_NF(GPP_B02, NONE, DEEP, NF3),
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
/* GPP_B03 : ISH_I2C0_SCL */
- PAD_CFG_NF(GPP_B03, NONE, DEEP, NF3),
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
/* GPP_D05 : ISH_UART_TX */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06 : ISH_UART_RX */
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Attention is currently required from: Jakub Czapiga, Paul Menzel, Subrata Banik.
Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78177?usp=email
to look at the new patch set (#7).
Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table
......................................................................
soc/intel: separate slp-s0 residency counter frequency in LPIT table
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform
Low Power Idle states. There are two types of low power residencies
a) CPU PKG C10 - read via MSR (Function fixed hardware interface)
b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO
Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_…,
section 2.2.1: value of 0 indicates that counter runs at TSC frequency.
Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4)
MSR 0x632: PC10 residency counter is at same frequency as the TSC.
Whereas slp_s0 residency counter running in different frequency.
BUG=b:300440936
TEST=check kernel cpuidle sysfs are created after kernel boot
cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
Change-Id: Ibde764551a21b9aecb1c269948f4823548294711
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/include/acpi/acpi.h
M src/soc/intel/common/block/acpi/lpit.c
2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/7
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