Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75836?usp=email )
Change subject: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0
......................................................................
mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0
It's been decided not to use any of the USB 3.0 ports on this board.
This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595fe
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").
BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.
Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Felix Singer: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
index 16f4375..9a0142c 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
@@ -20,7 +20,7 @@
}"
# USB related UPDs
- register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135
+ register "usb2_ports[0]" = "USB2_PORT_EMPTY" # UNUSED
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # UNUSED
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155
@@ -31,7 +31,7 @@
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
+ register "usb3_ports[0]" = "USB3_PORT_EMPTY" # UNUSED
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # UNUSED
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED
--
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Gerrit-Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Gerrit-Change-Number: 75836
Gerrit-PatchSet: 3
Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76177?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/siemens/mc_apl1: Fix wrong register masking
......................................................................
mb/siemens/mc_apl1: Fix wrong register masking
With the previous instruction the complete register was set to '0'.
Correctly, only the bits 23:16 must be masked.
Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
Jan Samek: Looks good to me, approved
Eric Lai: Looks good to me, approved
Felix Singer: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index b7b997b..8490ddc 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -12,6 +12,7 @@
#include <types.h>
#define TX_DWORD3_P1 0xa8c
+#define TX_SWING_MASK 0x00ff0000
void variant_mainboard_final(void)
{
@@ -42,10 +43,10 @@
/*
* Correct the SATA transmit signal via the High Speed I/O Transmit
* Control Register 3 on SATA port 1.
- * Bit [23:16] set the output voltage swing for TX line.
+ * Bit [23:16] sets the output voltage swing for TX line.
* The value 0x4a sets the swing level to 0.58 V.
*/
- pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, (0x00 << 16), (0x4a << 16));
+ pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, ~TX_SWING_MASK, 0x4a << 16);
}
static void finalize_boot(void *unused)
--
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Gerrit-Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Gerrit-Change-Number: 76177
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email )
Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
......................................................................
mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
1 file changed, 11 insertions(+), 0 deletions(-)
Approvals:
Jan Samek: Looks good to me, approved
build bot (Jenkins): Verified
Felix Singer: Looks good to me, but someone else must approve
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
index 1e7fa37..8eedce6 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
@@ -13,6 +13,9 @@
#include <baseboard/variants.h>
#include <types.h>
+#define TX_DWORD3_P0 0xc8c
+#define TX_SWING_MASK 0x00ff0000
+
void variant_mainboard_final(void)
{
struct device *dev = NULL;
@@ -32,6 +35,14 @@
*/
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+ /*
+ * Correct the SATA transmit signal via the High Speed I/O Transmit
+ * Control Register 3 on SATA port 0.
+ * Bit [23:16] sets the output voltage swing for TX line.
+ * The value 0x5a sets the swing level to 0.7 V.
+ */
+ pcr_rmw32(PID_MODPHY, TX_DWORD3_P0, ~TX_SWING_MASK, 0x5a << 16);
+
/* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) {
--
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Gerrit-Change-Number: 76175
Gerrit-PatchSet: 5
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76174?usp=email )
Change subject: mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'
......................................................................
mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3
refers to SATA port 1 only. To make this clear, change the name of the
define from 'TX_DWORD3' to 'TX_DWORD3_P1'.
Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jan Samek: Looks good to me, approved
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index c9d4b29..b7b997b 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -11,7 +11,7 @@
#include <baseboard/variants.h>
#include <types.h>
-#define TX_DWORD3 0xa8c
+#define TX_DWORD3_P1 0xa8c
void variant_mainboard_final(void)
{
@@ -41,11 +41,11 @@
/*
* Correct the SATA transmit signal via the High Speed I/O Transmit
- * Control Register 3.
+ * Control Register 3 on SATA port 1.
* Bit [23:16] set the output voltage swing for TX line.
* The value 0x4a sets the swing level to 0.58 V.
*/
- pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
+ pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, (0x00 << 16), (0x4a << 16));
}
static void finalize_boot(void *unused)
--
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Gerrit-Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Gerrit-Change-Number: 76174
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76173?usp=email )
Change subject: mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro
......................................................................
mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.
Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
3 files changed, 0 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, but someone else must approve
Jan Samek: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index c17f1be..b61f32d 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -14,8 +14,6 @@
#include <baseboard/variants.h>
#include <types.h>
-#define TX_DWORD3 0xa8c
-
void variant_mainboard_final(void)
{
struct device *dev = NULL;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
index 7362a48..1e7fa37 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
@@ -13,8 +13,6 @@
#include <baseboard/variants.h>
#include <types.h>
-#define TX_DWORD3 0xa8c
-
void variant_mainboard_final(void)
{
struct device *dev = NULL;
@@ -34,11 +32,6 @@
*/
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
- /* Correct the SATA transmit signal via the High Speed I/O Transmit Control Register 3.
- Bit [23:16] set the output voltage swing for TX line. The value 0x4a sets the swing
- level to 0.58 V. */
- pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
-
/* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) {
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
index b5aa068..1856a35 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
@@ -14,8 +14,6 @@
#include <baseboard/variants.h>
#include <types.h>
-#define TX_DWORD3 0xa8c
-
void variant_mainboard_final(void)
{
struct device *dev = NULL;
--
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Gerrit-Change-Number: 76173
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76144?usp=email )
Change subject: mb/google/nissa/var/joxer: support for different WiFi SAR tables
......................................................................
mb/google/nissa/var/joxer: support for different WiFi SAR tables
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table.
BUG=b:285477026
TEST=emerge-nissa coreboot and check the SAR value
Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com>
Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/joxer/overridetree.cb
M src/mainboard/google/brya/variants/joxer/variant.c
2 files changed, 8 insertions(+), 1 deletion(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Derek Huang: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb
index dbfeb6d..8ec3b21 100644
--- a/src/mainboard/google/brya/variants/joxer/overridetree.cb
+++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb
@@ -1,3 +1,10 @@
+fw_config
+ field WIFI_SAR_ID 6 6
+ option WIFI_GFP2_SAR_ID_0 0
+ option WIFI_GFP2_SAR_ID_1 1
+ end
+end
+
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/brya/variants/joxer/variant.c b/src/mainboard/google/brya/variants/joxer/variant.c
index 7db0617..3c23dd1 100644
--- a/src/mainboard/google/brya/variants/joxer/variant.c
+++ b/src/mainboard/google/brya/variants/joxer/variant.c
@@ -9,7 +9,7 @@
const char *get_wifi_sar_cbfs_filename(void)
{
- return "wifi_sar_0.hex";
+ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
}
void variant_devtree_update(void)
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75323?usp=email )
Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
......................................................................
mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:283245785
BRANCH=firmware-grunt-11031.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Edward Hill <ecgh(a)chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Eric Lai: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Edward Hill: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h
index aa5041b..56a6a4a 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h
@@ -20,7 +20,8 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Gerrit-Change-Number: 75323
Gerrit-PatchSet: 4
Gerrit-Owner: Rob Barnes <robbarnes(a)google.com>
Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org>
Gerrit-Reviewer: Edward Hill <ecgh(a)google.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76137?usp=email )
Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010
......................................................................
mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010
This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the kb8010 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The kb8010 retimer does not support this
feature, so let the SoC do the flip.
BUG=b:267589112
TEST=verified DP-ALT mode works in both cable orientations on rex with
reworked kb8010 DB by flykt@
Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/mainboard/google/rex/variants/rex0/variant.c
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/rex0/variant.c b/src/mainboard/google/rex/variants/rex0/variant.c
index 032eef9..8cf8ce2 100644
--- a/src/mainboard/google/rex/variants/rex0/variant.c
+++ b/src/mainboard/google/rex/variants/rex0/variant.c
@@ -31,7 +31,8 @@
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
MAX98360_ALC5682I_I2S));
- if (fw_config_probe(FW_CONFIG(DB_USB, USB4_ANX7452)) ||
+ if (fw_config_probe(FW_CONFIG(DB_USB, USB4_KB8010)) ||
+ fw_config_probe(FW_CONFIG(DB_USB, USB4_ANX7452)) ||
fw_config_probe(FW_CONFIG(DB_USB, USB4_ANX7452_V2))) {
/*
* Configure TCP2 for
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Gerrit-Change-Number: 76137
Gerrit-PatchSet: 2
Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75874?usp=email )
Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
mb/google/kahlee: Enable Secure OS
Secure OS was disabled on Grunt devices since it isn't used.
This reduces the attack surface and is meant to mitigate potential
security risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.
BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881
Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/google/kahlee/Kconfig
1 file changed, 4 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 8c8486e..3507181 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -145,8 +145,10 @@
endif
-# Don't use AMD's Secure OS
+# Don't use AMD's Secure OS if ChromeOS build.
config USE_PSPSECUREOS
- def_bool n
+ bool
+ default n if CHROMEOS
+ default y
endif # BOARD_GOOGLE_BASEBOARD_KAHLEE
--
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Gerrit-Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Gerrit-Change-Number: 75874
Gerrit-PatchSet: 10
Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com>
Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged