coreboot-gerrit July 2023

coreboot-gerrit@coreboot.org

1 participants
4441 discussions

[XS] Change in coreboot[master]: mb/system76/adl: Remove PL4 values
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75333?usp=email ) Change subject: mb/system76/adl: Remove PL4 values ...................................................................... mb/system76/adl: Remove PL4 values System76 EC since system76/ec@99dfbeaec3b8 sets PL4 values through PECI based on AC state for all boards. Remove the static PL4 values from coreboot since they won't be used. Ref: https://github.com/system76/ec/pull/353 Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333 Reviewed-by: Jeremy Soller <jeremy(a)system76.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/adl/variants/darp8/overridetree.cb M src/mainboard/system76/adl/variants/galp6/overridetree.cb M src/mainboard/system76/adl/variants/lemp11/overridetree.cb M src/mainboard/system76/adl/variants/oryp10/overridetree.cb M src/mainboard/system76/adl/variants/oryp9/overridetree.cb 5 files changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index a4dbed8..91b0291 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,10 +1,7 @@ chip soc/intel/alderlake - # HACK: Limit PL4 to PL2 to prevent power-off when system is booted on - # battery power. This seems to only happen with the i7 units. register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, - .tdp_pl4 = 56, // FIXME: Set to 65 }" # GPE configuration diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb index cac4df6..dc5d593 100644 --- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb @@ -2,7 +2,6 @@ register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 60, - .tdp_pl4 = 90, }" # GPE configuration diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb index 82943cb..379dad8 100644 --- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -2,7 +2,6 @@ register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 46, - .tdp_pl4 = 65, }" # GPE configuration diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index ddf5876..ad75a13 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -1,10 +1,8 @@ chip soc/intel/alderlake - # HACK: Limit PL4 to prevent power off on battery power. register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_psyspl2 = 135, - .tdp_pl4 = 72, }" # Thermal diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index a58c4c3..13989cb 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -1,10 +1,8 @@ chip soc/intel/alderlake - # HACK: Limit PL4 to prevent power off on battery power. register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_psyspl2 = 135, - .tdp_pl4 = 72, }" # Thermal -- To view, visit https://review.coreboot.org/c/coreboot/+/75333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189 Gerrit-Change-Number: 75333 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: ec/system76/ec: Do not call reset on wake
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75275?usp=email ) Change subject: ec/system76/ec: Do not call reset on wake ...................................................................... ec/system76/ec: Do not call reset on wake Resetting the device will cause the keyboard backlight and airplane LED to lose their state. Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275 Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/system76/ec/acpi/ec.asl 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: Jonathon Hall: Looks good to me, but someone else must approve Jeremy Soller: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index 21d9ad0..911a502 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -90,9 +90,6 @@ // Notify of changes Notify(^^^^AC, 0) Notify(^^^^BAT0, 0) - - // Reset System76 Device - ^^^^S76D.RSET() } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f Gerrit-Change-Number: 75275 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/system76/rpl: Add Oryx Pro 11 as a variant
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73976?usp=email ) Change subject: mb/system76/rpl: Add Oryx Pro 11 as a variant ...................................................................... mb/system76/rpl: Add Oryx Pro 11 as a variant The Oryx Pro 11 (oryp11) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots - Both M.2 NVMe SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73976 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp11.md M src/mainboard/system76/rpl/Kconfig M src/mainboard/system76/rpl/Kconfig.name M src/mainboard/system76/rpl/dsdt.asl A src/mainboard/system76/rpl/variants/oryp11/board.fmd A src/mainboard/system76/rpl/variants/oryp11/board_info.txt A src/mainboard/system76/rpl/variants/oryp11/data.vbt A src/mainboard/system76/rpl/variants/oryp11/gpio.c A src/mainboard/system76/rpl/variants/oryp11/gpio_early.c A src/mainboard/system76/rpl/variants/oryp11/hda_verb.c A src/mainboard/system76/rpl/variants/oryp11/overridetree.cb A src/mainboard/system76/rpl/variants/oryp11/romstage.c 13 files changed, 730 insertions(+), 0 deletions(-) Approvals: Jeremy Soller: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 06c60cb..8278bbf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -225,6 +225,7 @@ - [Oryx Pro 8](system76/oryp8.md) - [Oryx Pro 9](system76/oryp9.md) - [Oryx Pro 10](system76/oryp10.md) +- [Oryx Pro 11](system76/oryp11.md) ## Texas Instruments diff --git a/Documentation/mainboard/system76/oryp11.md b/Documentation/mainboard/system76/oryp11.md new file mode 100644 index 0000000..ad0a54e --- /dev/null +++ b/Documentation/mainboard/system76/oryp11.md @@ -0,0 +1,66 @@ +# System76 Oryx Pro 11 (oryp11) + +## Specs + +- CPU + - Intel Core i9-13900H +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options: + - NVIDIA GeForce RTX 4050 + - NVIDIA GeForce RTX 4060 + - NVIDIA GeForce RTX 4070 + - 16" 1920x1200@165Hz LCD + - External outputs: + - 1x HDMI 2.1 + - 1x Mini DisplayPort 1.4 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz +- Networking + - Realtek RTL8125BG-CG 2.5G Ethernet + - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211) +- Power + - 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86) + - 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73) +- Sound + - Realtek ALC1220 codec + - Realtek ALC1318 smart amp + - Internal speakers and microphone + - Combined 3.5mm headphone & microphone jack + - Combined 3.5mm microphone & S/PDIF jack + - HDMI, mDP, USB-C DP audio +- Storage + - 2x M.2 PCIe NVMe Gen 4 SSD + - MicroSD card reader (Realtek RTS5227S) +- USB + - 1x USB Type-C with Thunderbolt 4 + - 1x USB 3.2 Gen 2 Type-C + - 2x USB 2.1 Gen 1 Type-A +- Dimensions + - 35.95cm x 27.3cm x 1.99cm, 2.7kg + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | GigaDevice | ++---------------------+---------------------+ +| Model | GD25B256E | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The flash chip (U61) is left of the memory slots. diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index b2058d4..f3f56e7 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -26,6 +26,13 @@ select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P +config BOARD_SYSTEM76_ORYP11 + select BOARD_SYSTEM76_RPL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + if BOARD_SYSTEM76_RPL_COMMON config MAINBOARD_DIR @@ -33,18 +40,22 @@ config VARIANT_DIR default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Gazelle" if BOARD_SYSTEM76_GAZE18 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 config MAINBOARD_VERSION default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config CONSOLE_POST default y diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index 5bccbd2..aa267e7 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_SYSTEM76_GAZE18 bool "gaze18" + +config BOARD_SYSTEM76_ORYP11 + bool "oryp11" diff --git a/src/mainboard/system76/rpl/dsdt.asl b/src/mainboard/system76/rpl/dsdt.asl index df4681b..addb4df 100644 --- a/src/mainboard/system76/rpl/dsdt.asl +++ b/src/mainboard/system76/rpl/dsdt.asl @@ -19,6 +19,9 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> + #if CONFIG(BOARD_SYSTEM76_ORYP11) + #include <soc/intel/alderlake/acpi/tcss.asl> + #endif // CONFIG(BOARD_SYSTEM76_ORYP11) } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/rpl/variants/oryp11/board.fmd b/src/mainboard/system76/rpl/variants/oryp11/board.fmd new file mode 100644 index 0000000..fdf1ebd --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 4824K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/board_info.txt b/src/mainboard/system76/rpl/variants/oryp11/board_info.txt new file mode 100644 index 0000000..37f71e1 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp11 +Release year: 2023 diff --git a/src/mainboard/system76/rpl/variants/oryp11/data.vbt b/src/mainboard/system76/rpl/variants/oryp11/data.vbt new file mode 100644 index 0000000..bc9a931 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/data.vbt Binary files differ diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio.c b/src/mainboard/system76/rpl/variants/oryp11/gpio.c new file mode 100644 index 0000000..74fbde8 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // PCH_LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_GPO(GPD11, 1, DEEP), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0 + PAD_CFG_GPO(GPP_A6, 1, DEEP), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_CFG_GPO(GPP_A8, 1, DEEP), // GPP_A8 + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_CFG_GPO(GPP_A11, 1, DEEP), + PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + _PAD_CFG_STRUCT(GPP_A15, 0x86880100, 0x0000), // G_DP_A_HPD_L + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + _PAD_CFG_STRUCT(GPP_A18, 0x86880100, 0x0000), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_A20, 1, DEEP), // DGPU_OVRM + PAD_CFG_GPO(GPP_A21, 1, DEEP), // GPIO_LANRTD3 + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_PCH) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + _PAD_CFG_STRUCT(GPP_B5, 0x44000a01, 0x0000), // GPPB_I2C2_SDA + _PAD_CFG_STRUCT(GPP_B6, 0x44000a01, 0x0000), // GPPB_I2C2_SCL + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), // GPP_B11 + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // SYS_RESET# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // GPP_B14 + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18 + PAD_CFG_GPO(GPP_B19, 1, DEEP), + PAD_CFG_GPO(GPP_B20, 1, DEEP), + PAD_CFG_GPO(GPP_B21, 1, DEEP), + PAD_CFG_GPO(GPP_B22, 1, DEEP), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23 + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_SSD1_PWR_EN + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5 + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPO(GPP_D4, 0, DEEP), // PS8461_SW + // GPP_D5 (PEX_SSD2_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D6, 1, DEEP), + // GPP_D7 (WLAN_CLKREQ#) configured by FSP + // GPP_D8 (PEG_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D9, 1, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), // GPP_D10 + _PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x3c00), + PAD_CFG_GPO(GPP_D12, 0, DEEP), // GPP_D12 + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_W AKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_SSD2_PWR_EN + PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D19, 1, DEEP), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_W AKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + PAD_CFG_GPO(GPP_E5, 0, DEEP), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6 + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPO(GPP_E10, 1, DEEP), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_E12, 1, DEEP), + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD + PAD_CFG_GPO(GPP_E15, 1, DEEP), // CCD_FW_WP# + PAD_CFG_GPO(GPP_E16, 1, DEEP), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NATIVE), // GPP_E18_TBT_LSX0_TXD + PAD_NC(GPP_E19, NATIVE), // GPP_E19_TBT_LSX0_RXD + PAD_CFG_GPO(GPP_E20, 1, DEEP), + PAD_CFG_GPO(GPP_E21, 0, DEEP), // GPP_E21 + PAD_CFG_GPO(GPP_E22, 1, DEEP), + PAD_CFG_GPO(GPP_E23, 1, DEEP), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST# + // GPP_F5 (XTAL_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST# + PAD_CFG_GPO(GPP_F8, 1, DEEP), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_CFG_GPO(GPP_F10, 0, DEEP), // GPP_F10 + PAD_CFG_GPO(GPP_F11, 1, DEEP), + PAD_CFG_GPI(GPP_F12, NONE, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_F14, 1, DEEP), + PAD_CFG_GPO(GPP_F15, 1, DEEP), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_CFG_GPO(GPP_F17, 1, DEEP), + PAD_CFG_GPO(GPP_F18, 1, DEEP), + // GPP_F19 (LAN_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST# + PAD_CFG_GPO(GPP_F21, 1, DEEP), + PAD_CFG_GPO(GPP_F22, 1, DEEP), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), // GPP_H0 + PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M2_SSD1_RST# + PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M2_WLAN_RST# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RXD) configured in bootblock + // GPP_H11 (UART0_TXD) configured in bootblock + PAD_CFG_GPO(GPP_H12, 1, DEEP), + PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H15, 1, DEEP), + PAD_CFG_GPO(GPP_H16, 1, DEEP), + PAD_CFG_GPO(GPP_H17, 1, DEEP), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // PEX_SSD1_CLKREQ# + PAD_CFG_GPI(GPP_H20, NONE, DEEP), + PAD_CFG_GPI(GPP_H21, NONE, DEEP), + PAD_CFG_GPO(GPP_H22, 0, DEEP), + // GPP_H23 (CARD_CLKREQ#) configured by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_CFG_GPO(GPP_R5, 1, DEEP), + PAD_CFG_GPO(GPP_R6, 1, DEEP), + PAD_CFG_GPO(GPP_R7, 1, DEEP), + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPO(GPP_S0, 1, DEEP), + PAD_CFG_GPO(GPP_S1, 1, DEEP), + PAD_CFG_GPO(GPP_S2, 1, DEEP), + PAD_CFG_GPO(GPP_S3, 1, DEEP), + PAD_CFG_GPO(GPP_S4, 1, DEEP), + PAD_CFG_GPO(GPP_S5, 1, DEEP), + PAD_CFG_GPO(GPP_S6, 1, DEEP), + PAD_CFG_GPO(GPP_S7, 1, DEEP), + + /* ------- GPIO Group GPP_T ------- */ + PAD_CFG_GPO(GPP_T2, 1, DEEP), + PAD_CFG_GPO(GPP_T3, 1, DEEP), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c new file mode 100644 index 0000000..85b9307 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c new file mode 100644 index 0000000..dbed36f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155866a2, /* Subsystem ID */ + 243, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + AZALIA_SUBVENDOR(0, 0x155866a2), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60120), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + // ALC1318 smart amp + 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, + 0x02050058, 0x02048ed1, 0x02050063, 0x0204e430, + 0x02050016, 0x02048020, 0x02050016, 0x02048020, + 0x02050043, 0x02043005, 0x02050058, 0x02048ed1, + 0x02050063, 0x0204e430, 0x05b50000, 0x05b43530, + 0x05750002, 0x05741400, 0x05b5000a, 0x05b45520, + 0x02050042, 0x020486cb, 0x0143b000, 0x01470740, + 0x02050036, 0x02042a6a, 0x02050008, 0x0204800b, + 0x02050007, 0x020403c3, 0x01470c02, 0x01470c02, + 0x00c37100, 0x01b3b000, 0x01b70740, 0x00b37417, + 0x0205001b, 0x02044002, 0x0205001b, 0x02044002, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c000, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f20d, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f212, 0x0205002b, 0x0204003e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c001, + 0x0205002b, 0x02040002, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c003, 0x0205002b, 0x02040022, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c004, + 0x0205002b, 0x02040044, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c005, 0x0205002b, 0x02040044, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c007, + 0x0205002b, 0x02040064, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c00e, 0x0205002b, 0x020400e7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f223, + 0x0205002b, 0x0204007f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f224, 0x0205002b, 0x020400db, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f225, + 0x0205002b, 0x020400ee, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f226, 0x0205002b, 0x0204003f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f227, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f21a, 0x0205002b, 0x02040078, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f242, + 0x0205002b, 0x0204003c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c120, 0x0205002b, 0x02040040, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c321, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c200, + 0x0205002b, 0x020400d8, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c201, 0x0205002b, 0x02040027, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c202, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c400, 0x0205002b, 0x0204000e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c401, + 0x0205002b, 0x02040043, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c402, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c403, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c404, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c406, + 0x0205002b, 0x02040040, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c407, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c408, + 0x0205002b, 0x0204003f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c300, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df00, 0x0205002b, 0x02040010, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204df5f, + 0x0205002b, 0x02040001, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df60, 0x0205002b, 0x020400a7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ea00, + 0x0205002b, 0x02040047, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c203, 0x0205002b, 0x02040084, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c206, + 0x0205002b, 0x02040078, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x02040065, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e706, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e707, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e806, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e807, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce60, 0x0205002b, 0x020400e3, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c130, + 0x0205002b, 0x02040051, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e000, 0x0205002b, 0x020400a8, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02044100, 0x02050029, 0x02041888, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c121, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, + + // XXX: Duplicate last 2 u32s to keep in 4-dword blocks + 0x0205002c, 0x0204b423, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb new file mode 100644 index 0000000..8c5315b --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -0,0 +1,97 @@ +chip soc/intel/alderlake + device domain 0 on + subsystemid 0x1558 0x66a2 inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + end + device ref tcss_dma0 on end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # AJ_USB1: USB-A 3.2 Gen 1 (Left) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1: USB-C Thunderbolt (Right) + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1: USB-A 3.2 Gen 1 (Right) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB1: USB-A 3.2 Gen 1 (Left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1: USB-A 3.2 Gen 1 (Right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # CPU PCIe RP#2 x8, Clock 3 (GPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie4_0 on + # CPU RP#1 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie4_1 on + # PCIE RP#3 x4, Clock 4 (SSD1) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp5 on + # PCH RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 on + # PCH RP#6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp7 on + # PCH RP#7 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + end +end diff --git a/src/mainboard/system76/rpl/variants/oryp11/romstage.c b/src/mainboard/system76/rpl/variants/oryp11/romstage.c new file mode 100644 index 0000000..1e597c7 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e Gerrit-Change-Number: 73976 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73689?usp=email ) Change subject: mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI ...................................................................... mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI This allows the EC to detect C10 using eSPI instead of a dedicated pin. Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/tgl-u/variants/darp7/ramstage.c M src/mainboard/system76/tgl-u/variants/galp5/ramstage.c M src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c 3 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c index a60587d..2b64f9f 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -12,4 +12,7 @@ // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c index a60587d..2b64f9f 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -12,4 +12,7 @@ // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c index 2064836..8b80740 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -12,4 +12,7 @@ // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[2] = 1; // J_TYPEC1 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/73689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494 Gerrit-Change-Number: 73689 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XL] Change in coreboot[master]: mb/system76/adl: Add Gazelle 17 as a variant
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63990?usp=email ) Change subject: mb/system76/adl: Add Gazelle 17 as a variant ...................................................................... mb/system76/adl: Add Gazelle 17 as a variant The gaze17 comes in 2 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet Controller - NVIDIA RTX 3060, using onboard I219-V Ethernet Controller Tested with a custom TianoCore UefiPayloadPkg payload. Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - MicroSD card reader - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting to Pop!_OS Linux 22.04 with kernel 6.2.6 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - Discrete/Hybrid graphics: Requires NVIDIA driver - mDP/HDMI displays on 3060 variant: Requires NVIDIA driver - Detection of devices in TBT slot on boot - S3 suspend: MP init eventually fails Not tested: - Thunderbolt devices Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63990 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/gaze17.md M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/adl/Kconfig.name A src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt A src/mainboard/system76/adl/variants/gaze17-3050/data.vbt A src/mainboard/system76/adl/variants/gaze17-3050/gpio.c A src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c A src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c A src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb A src/mainboard/system76/adl/variants/gaze17-3050/romstage.c A src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt A src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt A src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c A src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c A src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c A src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb A src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c 18 files changed, 1,023 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 59e91d4..06c60cb 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -214,6 +214,7 @@ - [Galago Pro 6](system76/galp6.md) - [Gazelle 15](system76/gaze15.md) - [Gazelle 16](system76/gaze16.md) +- [Gazelle 17](system76/gaze17.md) - [Gazelle 18](system76/gaze18.md) - [Lemur Pro 9](system76/lemp9.md) - [Lemur Pro 10](system76/lemp10.md) diff --git a/Documentation/mainboard/system76/gaze17.md b/Documentation/mainboard/system76/gaze17.md new file mode 100644 index 0000000..cf7f0a2 --- /dev/null +++ b/Documentation/mainboard/system76/gaze17.md @@ -0,0 +1,65 @@ +# System76 Gazelle 17 (gaze17) + +The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b. + +## Specs + +- CPU + - Intel Core i5-12500H + - Intel Core i7-12700H +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options + - NVIDIA GeForce RTX 3050 + - NVIDIA GeForce RTX 3050 Ti + - NVIDIA GeForce RTX 3060 +- Memory + - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s +- Networking + - Gigabit Ethernet + - 3050: Realtek RTL8111H controller + - 3060: Onboard Intel I219-V + - M.2 PCIe/CNVi WiFi/Bluetooth + - Intel Wi-Fi 6 AX201 +- Power + - 3050: 150W (20V, 7.5A) AC barrel adapter + - 3060: 180W (20V, 9A) AC barrel adapter + - Lite-On PA-1181-76, using a C5 power cord + - 54Wh 4-cell Li-ion battery (NP50BAT-4-54) +- Sound + - Realtek ALC256 codec + - Internal speakers and microphone + - Combined 3.5mm headphone/microphone jack + - Dedicated 3.5mm microphone jack +- Storage + - 1x M.2 PCIe NVMe Gen 4 SSD + - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD + - MicroSD card reader (Realtek RTS5227S/OZ711LV2) + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | GigaDevice | ++---------------------+---------------------+ +| Model | GD25B256E | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The position of the flash chip depends on the variant: + +- 3050: U24, below the bottom DIMM slot. +- 3060: U55, left of the PCIe 4.0 M.2 slot. diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 83176d1..e505ebb 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -1,19 +1,13 @@ -if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_SYSTEM76_ADL_COMMON + def_bool n select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_HID select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER - select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9 select EC_SYSTEM76_EC - select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 - select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE - select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11 select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_TPM2 @@ -26,12 +20,49 @@ select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_SYSTEM76_DARP8 + select BOARD_SYSTEM76_ADL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + +config BOARD_SYSTEM76_GALP6 + select BOARD_SYSTEM76_ADL_COMMON + +config BOARD_SYSTEM76_GAZE17_3050 + select BOARD_SYSTEM76_ADL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + +config BOARD_SYSTEM76_GAZE17_3060_B + select BOARD_SYSTEM76_ADL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_SYSTEM76_LEMP11 + select BOARD_SYSTEM76_ADL_COMMON + select HAVE_SPD_IN_CBFS + +config BOARD_SYSTEM76_ORYP9 + select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_I2C_TAS5825M + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + +config BOARD_SYSTEM76_ORYP10 + select BOARD_SYSTEM76_ADL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + +if BOARD_SYSTEM76_ADL_COMMON + config MAINBOARD_DIR default "system76/adl" config VARIANT_DIR default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050 + default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 @@ -42,6 +73,8 @@ config MAINBOARD_PART_NUMBER default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050 + default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 @@ -49,12 +82,15 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 default "Galago Pro" if BOARD_SYSTEM76_GALP6 + default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B default "Lemur Pro" if BOARD_SYSTEM76_LEMP11 default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050 + default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name index ee7b6ff..99d7ea0 100644 --- a/src/mainboard/system76/adl/Kconfig.name +++ b/src/mainboard/system76/adl/Kconfig.name @@ -4,6 +4,12 @@ config BOARD_SYSTEM76_GALP6 bool "galp6" +config BOARD_SYSTEM76_GAZE17_3050 + bool "gaze17 3050" + +config BOARD_SYSTEM76_GAZE17_3060_B + bool "gaze17 3060-b" + config BOARD_SYSTEM76_LEMP11 bool "lemp11" diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt b/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt new file mode 100644 index 0000000..926fe4e --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze17-3050 +Release year: 2022 diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt b/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt new file mode 100644 index 0000000..c0531fd --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c new file mode 100644 index 0000000..a30eec1 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + //PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14 + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH + PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE# + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN + PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST# + //PAD_NC(GPP_B9, NONE), + //PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED# + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP + //PAD_NC(GPP_B19, NONE), + //PAD_NC(GPP_B20, NONE), + //PAD_NC(GPP_B21, NONE), + //PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2 + PAD_NC(GPP_C3, NONE), // SML0_CLK + PAD_NC(GPP_C4, NONE), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP + PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL + PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA + //PAD_NC(GPP_C8, NONE), + //PAD_NC(GPP_C9, NONE), + //PAD_NC(GPP_C10, NONE), + //PAD_NC(GPP_C11, NONE), + //PAD_NC(GPP_C12, NONE), + //PAD_NC(GPP_C13, NONE), + //PAD_NC(GPP_C14, NONE), + //PAD_NC(GPP_C15, NONE), + //PAD_NC(GPP_C16, NONE), + //PAD_NC(GPP_C17, NONE), + //PAD_NC(GPP_C18, NONE), + //PAD_NC(GPP_C19, NONE), + //PAD_NC(GPP_C20, NONE), + //PAD_NC(GPP_C21, NONE), + //PAD_NC(GPP_C22, NONE), + //PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN + //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ# + //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ# + //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ# + //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ# + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 + PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE# + PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN# + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + //_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_NC(GPP_E12, NONE), + PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), + //PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST# + PAD_NC(GPP_F11, NONE), // ADDS_CODE + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET# + PAD_NC(GPP_F15, NONE), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ# + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1# + PAD_NC(GPP_F21, NONE), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2# + PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA + PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL + PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + //PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + //PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + PAD_NC(GPP_H12, NONE), + _PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1 + //PAD_NC(GPP_H14, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK + //PAD_NC(GPP_H16, NONE), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ# + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), + PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK + PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c new file mode 100644 index 0000000..85b9307 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c new file mode 100644 index 0000000..337f469 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x1558866d, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558866d), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = { + // Adjust mic coefficient + 0x02050007, + 0x02040202, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb new file mode 100644 index 0000000..174c926 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -0,0 +1,154 @@ +chip soc/intel/alderlake + # FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Thermal + register "tcc_offset" = "10" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + + device domain 0 on + subsystemid 0x1558 0x866d inherit + + device ref pcie5_0 on + # PCIe PEG2 x8, Clock 3 (DGPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR, + }" + end + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 off end + device ref tbt_pcie_rp0 off end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + device ref tcss_root_hub on + device ref tcss_usb3_port1 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 + end + device ref pcie_rp5 on + # PCIe RP#5 x4, Clock 1 (SSD) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable tied to 3.3VS? + #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "disable_l23" = "true" + register "srcclk_pin" = "1" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable tied to VDD3? + #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "6" # GLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp10 on + # PCIe RP#10 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe RP#11 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable tied to 3.3VS? + #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ# + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c new file mode 100644 index 0000000..5e6cf7d --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt b/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt new file mode 100644 index 0000000..6352efb --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze17-3060-b +Release year: 2022 diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt b/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt new file mode 100644 index 0000000..4fe5dd0 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c new file mode 100644 index 0000000..07fa383 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16) + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE# + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0 + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + //PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + _PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE# + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + //PAD_CFG_GPO(GPP_B9, 0, DEEP), + //PAD_CFG_GPO(GPP_B10, 0, DEEP), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED# + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24 + //PAD_CFG_GPO(GPP_B19, 0, DEEP), + //PAD_CFG_GPO(GPP_B20, 0, DEEP), + //PAD_CFG_GPO(GPP_B21, 0, DEEP), + //PAD_CFG_GPO(GPP_B22, 0, DEEP), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24 + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1 + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24 + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA + //PAD_NC(GPP_C8, NONE), + //PAD_NC(GPP_C9, NONE), + //PAD_NC(GPP_C10, NONE), + //PAD_NC(GPP_C11, NONE), + //PAD_NC(GPP_C12, NONE), + //PAD_NC(GPP_C13, NONE), + //PAD_NC(GPP_C14, NONE), + //PAD_NC(GPP_C15, NONE), + //PAD_NC(GPP_C16, NONE), + //PAD_NC(GPP_C17, NONE), + //PAD_NC(GPP_C18, NONE), + //PAD_NC(GPP_C19, NONE), + //PAD_NC(GPP_C20, NONE), + //PAD_NC(GPP_C21, NONE), + //PAD_NC(GPP_C22, NONE), + //PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW + //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ# + //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ# + //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ# + //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ# + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24 + PAD_NC(GPP_D11, NONE), + PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24 + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2 + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + //_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24 + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN# + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD + PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD + PAD_NC(GPP_E20, NONE), + PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24 + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST# + //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST# + //PAD_CFG_GPO(GPP_F8, 0, DEEP), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST# + PAD_NC(GPP_F11, NONE), + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST# + PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24 + PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD + PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD + PAD_NC(GPP_H12, NONE), + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1 + //PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + //PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC + PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC + PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS + //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ# + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1 + PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1 + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c new file mode 100644 index 0000000..c2009a8 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c new file mode 100644 index 0000000..f28070c --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x1558867c, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558867c), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb new file mode 100644 index 0000000..a489bf2 --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -0,0 +1,155 @@ +chip soc/intel/alderlake + # FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Thermal + register "tcc_offset" = "10" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + + device domain 0 on + subsystemid 0x1558 0x867c inherit + + device ref pcie5_0 on + # PCIe PEG2 x8, Clock 3 (DGPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR, + }" + end + device ref igpu on + # DDIA is eDP + register "ddi_portA_config" = "1" + register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 off end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + device ref tcss_root_hub on + device ref tcss_usb3_port1 on end + end + end + device ref tcss_dma0 on end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B + end + device ref pcie_rp5 on + # PCIe root port #5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: No enable_gpio = no D3cold? + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 6 (GLAN) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 1 (SSD1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable tied to 3.3VS? + #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "disable_l23" = "true" # Fixes suspend on WD drives + register "srcclk_pin" = "1" # SSD_CLKREQ# + device generic 0 on end + end + end + device ref gbe on end + end +end diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c new file mode 100644 index 0000000..5e6cf7d --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7 Gerrit-Change-Number: 63990 Gerrit-PatchSet: 12 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/system76/tgl-h: Disable D3cold
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61980?usp=email ) Change subject: mb/system76/tgl-h: Disable D3cold ...................................................................... mb/system76/tgl-h: Disable D3cold Disable D3cold to prevent issues with Thunderbolt not working after S3 suspend. Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/tgl-h/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Jeremy Soller: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig index 7debee2..cefee16 100644 --- a/src/mainboard/system76/tgl-h/Kconfig +++ b/src/mainboard/system76/tgl-h/Kconfig @@ -74,4 +74,7 @@ config USE_PM_ACPI_TIMER default n +config D3COLD_SUPPORT + default n + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c Gerrit-Change-Number: 61980 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd/*: Utilize get_fmap_value() Makefile function where possible
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76168?usp=email ) Change subject: soc/amd/*: Utilize get_fmap_value() Makefile function where possible ...................................................................... soc/amd/*: Utilize get_fmap_value() Makefile function where possible Replace: $(shell awk '$$2 == "xyz" {print $$3}' $(obj)/fmap_config.h) with: $(call get_fmap_value,xyz) to improve code readability/maintainability. Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76168 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Makefile.inc 5 files changed, 39 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 062a19d..c4b23d1 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -59,12 +59,10 @@ AMD_FW_AB_POSITION := 0x40 CEZANNE_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) CEZANNE_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -130,8 +128,8 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 47c121e..c35c3fe 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -62,12 +62,10 @@ AMD_FW_AB_POSITION := 0x40 GLINDA_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) GLINDA_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -129,8 +127,8 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location @@ -146,11 +144,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index ac7ec6d..4661234 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -62,12 +62,10 @@ AMD_FW_AB_POSITION := 0x80 MENDOCINO_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) MENDOCINO_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) MENDOCINO_FW_BODY_OFFSET := 0x100 @@ -132,14 +130,14 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) else APOB_NV_RO_SIZE=$(APOB_NV_SIZE) APOB_NV_RO_BASE=$(APOB_NV_BASE) @@ -159,11 +157,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 0945830..0e42b98 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -65,12 +65,10 @@ AMD_FW_AB_POSITION := 0x40 PHOENIX_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) PHOENIX_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -132,21 +130,21 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) else APOB_NV_RO_SIZE=$(APOB_NV_SIZE) APOB_NV_RO_BASE=$(APOB_NV_BASE) endif ifeq ($(CONFIG_AMDFW_SPLIT),y) -FMAP_AMDFW_BODY_LOCATION=$(shell awk '$$2 == "FMAP_SECTION_AMDFWBODY_START" {print $$3}' $(obj)/fmap_config.h) +FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) endif ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) @@ -163,11 +161,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index cb42582..1d275b0 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -65,12 +65,10 @@ AMD_FW_AB_POSITION := 0x40 PICASSO_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) PICASSO_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items @@ -110,8 +108,8 @@ # type = 0x4 # The flashmap section used for this is expected to be named PSP_NVRAM -PSP_NVRAM_BASE=$(shell awk '$$2 == "FMAP_SECTION_PSP_NVRAM_START" {print $$3}' $(obj)/fmap_config.h) -PSP_NVRAM_SIZE=$(shell awk '$$2 == "FMAP_SECTION_PSP_NVRAM_SIZE" {print $$3}' $(obj)/fmap_config.h) +PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START) +PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE) # type = 0x7 # RSA 2048 signature @@ -132,8 +130,8 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location -- To view, visit https://review.coreboot.org/c/coreboot/+/76168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Gerrit-Change-Number: 76168 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd/*: Utilize get_fmap_value() Makefile function where possible
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Attention is currently required from: Eric Lai, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76168?usp=email ) Change subject: soc/amd/*: Utilize get_fmap_value() Makefile function where possible ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Gerrit-Change-Number: 76168 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Jul 2023 12:51:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: Makefile.inc: relocate get_fmap_value() here from soc/intel/common/bl...
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76167?usp=email ) Change subject: Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cse ...................................................................... Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cse Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved Julius Werner: Looks good to me, approved build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index ab57abd..9a34c61 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -146,6 +146,7 @@ # tolower: returns the value in all lowercase # toupper: returns the value in all uppercase # ws_to_under: returns the value with any whitespace changed to underscores +# get_fmap_value returns the value of a given FMAP field from fmap_config.h _toint=$(shell printf "%d" $1) _tohex=$(shell printf 0x"%x" $1) _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2)) @@ -165,6 +166,7 @@ tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') ws_to_under=$(shell echo '$1' | tr ' \t' '_') +get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h) ####################################################################### # Helper functions for ramstage postprocess diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 3e11279..ad15dc4 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -24,7 +24,6 @@ CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE)) CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE)) -get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h) get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET)) CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START) -- To view, visit https://review.coreboot.org/c/coreboot/+/76167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Gerrit-Change-Number: 76167 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5
by Felix Held (Code Review) 03 Jul '23

03 Jul '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75900?usp=email ) Change subject: mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5 ...................................................................... mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5 Update SX9324 register settings based on tuning value from SEMTECH. BUG=b:279510275 TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900 Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 74 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 9a822d6..6601247 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -460,6 +460,80 @@ probe LTE LTE_PRESENT end end + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x25" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x3f" + register "reg_afe_ph2" = "0x37" + register "reg_afe_ph3" = "0x3f" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x10" + register "reg_prox_ctrl7" = "0x0e" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0xff" + register "reg_adv_ctrl18" = "0x35" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x60" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 3, 3}" + register "ph2_pin" = "{3, 1, 3}" + register "ph3_pin" = "{3, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "3" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""gnd"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe WWAN_5G WWAN_5G_PRESENT + end + end + end device ref i2c3 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/75900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Gerrit-Change-Number: 75900 Gerrit-PatchSet: 10 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2023