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Change subject: soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset
......................................................................
soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset
Pass the APOB NV address as a flash offset instead of x86 address.
TEST=boot birman and verify APOB_NV is working
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc
---
M src/soc/amd/phoenix/Makefile.inc
1 file changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/76162/4
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Change subject: configs/config.raptor-cs-talos-2: add config for Talos-II
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67070/comment/1c9a5cbd_64dc875b :
PS14, Line 7: Talos-II
It’s spelled without a hyphen, isn’t it: Talos II [1]?
[1]: https://www.raptorcs.com/TALOSII/
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69798?usp=email )
Change subject: soc/intel/alderlake: Add support for Raptor Lake S CPUs
......................................................................
Patch Set 14:
(1 comment)
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/69798/comment/9cb7f24e_442554cb :
PS14, Line 76: #define CPUID_RAPTORLAKE_S_A0 0xb0670
: #define CPUID_RAPTORLAKE_S_B0 0xb0671
: #define CPUID_RAPTORLAKE_S_C0_1 0xb0672
: #define CPUID_RAPTORLAKE_S_C0_2 0xb0675
: #define CPUID_RAPTORLAKE_P_J0 0xb06a2
: #define CPUID_RAPTORLAKE_P_Q0 0xb06a3
> I think we can if we get it reported right in report_platform. […]
I would also drop the `-S`/`-P`/etc from them, like the ADL ones above it.
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Hello Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
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Change subject: [WIP] soc/intel/alderlake: Increase default CBFS size
......................................................................
[WIP] soc/intel/alderlake: Increase default CBFS size
Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/76217/2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76166?usp=email )
Change subject: soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATION
......................................................................
soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATION
Phoenix is an x86 soc that supports sha256 instructions.
TEST=boot birman to chromeos
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: Id228399ba02708b97110d524ce12c2626588762d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/soc/amd/phoenix/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index a9f124c..5f4e5d1 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -88,6 +88,7 @@
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
+ select VBOOT_X86_SHA256_ACCELERATION if VBOOT
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
help
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Change subject: amdfwtool: Allow bios table source addresses to select base
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
shouldn't this be done for all src, dest and size parameters to be consistent?
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