June 2023 - coreboot-gerrit - mail.coreboot.org

[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order
by Won Chung (Code Review) June 1, 2023

June 1, 2023

Attention is currently required from: Tarun Tuli. Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75572?usp=email ) Change subject: mb/google/brya/var/taeko: Fix PLD group order ...................................................................... mb/google/brya/var/taeko: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Signed-off-by: Won Chung <wonchung(a)google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/75572/1 diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index cdfd2ff..6a2b747 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -602,7 +602,7 @@ register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A @@ -626,7 +626,7 @@ register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A -- To view, visit https://review.coreboot.org/c/coreboot/+/75572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Gerrit-Change-Number: 75572 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/brya/var/marasov: Fix PLD group order
by Won Chung (Code Review) June 1, 2023

June 1, 2023

Attention is currently required from: Tarun Tuli. Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75571?usp=email ) Change subject: mb/google/brya/var/marasov: Fix PLD group order ...................................................................... mb/google/brya/var/marasov: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Signed-off-by: Won Chung <wonchung(a)google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75571/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 79d5abb..391dc5f 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -366,7 +366,7 @@ register "desc" = ""USB3 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port3 on end end @@ -387,7 +387,7 @@ register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/75571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Gerrit-Change-Number: 75571 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/brya/var/constitution: Fix PLD group order
by Won Chung (Code Review) June 1, 2023

June 1, 2023

Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75570?usp=email ) Change subject: mb/google/brya/var/constitution: Fix PLD group order ...................................................................... mb/google/brya/var/constitution: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Signed-off-by: Won Chung <wonchung(a)google.com> --- M src/mainboard/google/brya/variants/constitution/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/75570/1 diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 4b894b0..17965fd 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -244,14 +244,14 @@ register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -271,14 +271,14 @@ register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/75570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Gerrit-Change-Number: 75570 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Add codec RTL5682 and amp RTL1019
by Jon Murphy (Code Review) June 1, 2023

June 1, 2023

Attention is currently required from: Eric Lai, Karthik Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75477?usp=email ) Change subject: mb/google/myst: Add codec RTL5682 and amp RTL1019 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75477?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98 Gerrit-Change-Number: 75477 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 00:21:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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