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[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. Hello Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74938 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports ...................................................................... mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports This mainboard has three connected PCIe devices. This patch enables and configures the required root ports. Change-Id: I8f7ef1ac35d78a6d5863ffbbc367addd820f4004 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb 1 file changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74938/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f7ef1ac35d78a6d5863ffbbc367addd820f4004 Gerrit-Change-Number: 74938 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Disable PCIe RP7
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. Hello Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74937 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl5: Disable PCIe RP7 ...................................................................... mb/siemens/mc_ehl5: Disable PCIe RP7 This mainboard does not use legacy PCI devices behinde a PCIe-2-PCI bridge like the mc_ehl2 mainboard does. Therefore PCIe RP7 is disabled and all functionality for it is removed. Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c 3 files changed, 17 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74937/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443 Gerrit-Change-Number: 74937 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74938 ) Change subject: mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports ...................................................................... mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports This mainboard has three connected PCIe devices. This patch enables and configures the required root ports. Change-Id: I8f7ef1ac35d78a6d5863ffbbc367addd820f4004 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb 1 file changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74938/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 31002c0..76be791 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -41,13 +41,15 @@ # PCIe root ports related UPDs register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[4]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" @@ -58,9 +60,13 @@ # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[4]" = "true" # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" @@ -181,6 +187,8 @@ device pci 1a.1 on end # SD device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f7ef1ac35d78a6d5863ffbbc367addd820f4004 Gerrit-Change-Number: 74938 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Disable PCIe RP7
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74937 ) Change subject: mb/siemens/mc_ehl5: Disable PCIe RP7 ...................................................................... mb/siemens/mc_ehl5: Disable PCIe RP7 This mainboard does not use legacy PCI devices behinde a PCIe-2-PCI bridge like the mc_ehl2 mainboard does. Therfore PCIe RP7 is disabled and all functionality for it is removed. Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c 3 files changed, 17 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74937/1 diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index 7aa0d86..db72123 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -95,6 +95,9 @@ uint32_t legacy_delay, us_since_boot; struct stopwatch sw; + if (CONFIG(BOARD_SIEMENS_MC_EHL5)) + return; + /* Open main hwinfo block. */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) return; diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 53ea1f6..31002c0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -41,7 +41,6 @@ # PCIe root ports related UPDs register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -59,11 +58,9 @@ # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[1]" = "true" - register "PcieRpLtrDisable[6]" = "true" # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" @@ -184,7 +181,6 @@ device pci 1a.1 on end # SD device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c index 1121399..0930cae 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c @@ -21,15 +21,6 @@ { struct device *dev; - /* PIR8 register mapping for PCIe root ports - INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ - pcr_write16(PID_ITSS, 0x3150, 0x1032); - - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); -- To view, visit https://review.coreboot.org/c/coreboot/+/74937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443 Gerrit-Change-Number: 74937 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Disable PCIe RP7
by build bot (Jenkins) (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74937 ) Change subject: mb/siemens/mc_ehl5: Disable PCIe RP7 ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175447): https://review.coreboot.org/c/coreboot/+/74937/comment/626f24eb_7fff22f2 PS1, Line 9: This mainboard does not use legacy PCI devices behinde a PCIe-2-PCI 'Therfore' may be misspelled - perhaps 'Therefore'? -- To view, visit https://review.coreboot.org/c/coreboot/+/74937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443 Gerrit-Change-Number: 74937 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 03 May 2023 12:50:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridge
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74936 ) Change subject: mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridge ...................................................................... mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridge This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c 5 files changed, 127 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74936/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig index 1ad4ede..151d24a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig @@ -2,6 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select DRIVERS_I2C_PTN3460 select DRIVERS_I2C_RV3028C7 select DRIVER_INTEL_I210 select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc index 6e87f9f..be8ec05 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc @@ -3,4 +3,5 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += lcd_panel.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index f14c225..53ea1f6 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -106,6 +106,9 @@ register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE" register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + register "common_soc_config" = "{ .i2c[1] = { .speed = I2C_SPEED_STANDARD, @@ -158,12 +161,16 @@ end end device pci 15.2 on # I2C2 - # Add dummy I2C device to limit BUS speed to 100 kHz in OS + # Add dummy I2C device to limit BUS speed to 100 kHz in OS chip drivers/i2c/generic register "hid" = ""PRP0001"" register "speed" = "I2C_SPEED_STANDARD" device i2c 0x7f on end end + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x20 on end # PTN3460 DP2LVDS Bridge + end end device pci 15.3 on end # I2C3 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c index 20a89c6..c53f5e4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c @@ -134,7 +134,7 @@ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ PAD_NC(GPP_E18, NONE), /* Not connected */ - PAD_NC(GPP_E19, NONE), /* Not connected */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c new file mode 100644 index 0000000..0b68ed7 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/lcd_panel.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/i2c/ptn3460/ptn3460.h> +#include <hwilib.h> +#include <types.h> + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460). + * @param edid_data pointer to EDID data in driver + * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise + */ +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. + * @return Index of the EDID slot selected for EDID emulation + */ +uint8_t mainboard_ptn3460_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. For reference, + * see NXP document AN11128 - PTN3460 Programming guide. + * @param *cfg_ptr Pointer to the PTN config structure to modify + * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error + */ +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + /* Get display-specific configuration from hwinfo. */ + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return CB_ERR; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return CB_ERR; + } + + /* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */ + /* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */ + cfg->dp_interface_ctrl = 0x00; + /* Use odd bus for LVDS clock distribution only. */ + cfg->lvds_interface_ctrl1 = 0x01; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* No LVDS clock spreading, 300 mV LVDS swing */ + cfg->lvds_interface_ctrl2 = 0x03; + /* No LVDS lane/channel swapping */ + cfg->lvds_interface_ctrl3 = 0x00; + /* Enable VDD to LVDS active delay. */ + cfg->t2_delay = 0x01; + /* LVDS to backlight active delay: 200 ms */ + cfg->t3_timing = 0x04; + /* Minimum re-power delay: 500 ms */ + cfg->t12_timing = 0x0a; + /* Backlight off to LVDS inactive delay: 200 ms */ + cfg->t4_timing = 0x04; + /* Enable LVDS to VDD inactive delay. */ + cfg->t5_delay = 0x01; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0x00; + + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Gerrit-Change-Number: 74936 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2
by Mario Scheithauer (Code Review) 03 May '23

03 May '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74935 ) Change subject: mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2 ...................................................................... mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2 This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig M src/mainboard/siemens/mc_ehl/Kconfig.name A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c 8 files changed, 578 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74935/1 diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index 60757fe..89d53c7 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -21,12 +21,14 @@ default "mc_ehl2" if BOARD_SIEMENS_MC_EHL2 default "mc_ehl3" if BOARD_SIEMENS_MC_EHL3 default "mc_ehl4" if BOARD_SIEMENS_MC_EHL4 + default "mc_ehl5" if BOARD_SIEMENS_MC_EHL5 config MAINBOARD_PART_NUMBER default "MC EHL1" if BOARD_SIEMENS_MC_EHL1 default "MC EHL2" if BOARD_SIEMENS_MC_EHL2 default "MC EHL3" if BOARD_SIEMENS_MC_EHL3 default "MC EHL4" if BOARD_SIEMENS_MC_EHL4 + default "MC EHL5" if BOARD_SIEMENS_MC_EHL5 config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name index 2eead51..72dffc0 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig.name +++ b/src/mainboard/siemens/mc_ehl/Kconfig.name @@ -15,3 +15,7 @@ config BOARD_SIEMENS_MC_EHL4 bool "-> MC_EHL4" select BOARD_SIEMENS_BASEBOARD_MC_EHL + +config BOARD_SIEMENS_MC_EHL5 + bool "-> MC_EHL5" + select BOARD_SIEMENS_BASEBOARD_MC_EHL diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig new file mode 100644 index 0000000..1ad4ede --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig @@ -0,0 +1,22 @@ +if BOARD_SIEMENS_MC_EHL5 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select DRIVERS_I2C_RV3028C7 + select DRIVER_INTEL_I210 + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + select EHL_TSN_DRIVER + select DRIVERS_ETH_PHY_M88E1512 + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select TPM_MEASURED_BOOT + select TPM_MEASURED_BOOT_INIT_BOOTBLOCK + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" + +config UART_FOR_CONSOLE + int + default 0 + +endif # BOARD_SIEMENS_MC_EHL5 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc new file mode 100644 index 0000000..6e87f9f --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb new file mode 100644 index 0000000..f14c225 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -0,0 +1,250 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + + # Enable IBECC for the complete memory + register "ibecc" = "{ + .enable = 1, + .mode = IBECC_ALL + }" + + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB Panel + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB Panel + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED + + # Skip the CPU replacement check + register "SkipCpuReplacementCheck" = "1" + + # PCIe root ports related UPDs + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + + # Disable all L1 substates for PCIe root ports + register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" + + # Disable LTR for all PCIe root ports + register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[6]" = "true" + + # Storage (SDCARD/EMMC) related UPDs + register "ScsEmmcHs400Enabled" = "0" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C6] = PchSerialIoDisabled, + [PchSerialIoIndexI2C7] = PchSerialIoDisabled, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + + # TSN GBE related UPDs + register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps" + register "PchTsnGbeSgmiiEnable" = "1" + register "PseDmaOwn[0]" = "Host_Owned" + register "PseDmaOwn[1]" = "Host_Owned" + register "pch_tsn_phy_irq_edge" = "RISING_EDGE" + register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE" + register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE" + + register "common_soc_config" = "{ + .i2c[1] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, + }, + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1df, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, + }, + }" + + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + + # Disable L1 prefetcher for real-time demands + register "L1_prefetcher_disable" = "true" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + + device pci 14.0 on end # USB3.1 xHCI + + device pci 15.0 on end # I2C0 + device pci 15.1 on # I2C1 + # Enable external RTC chip + chip drivers/i2c/rv3028c7 + register "bus_speed" = "I2C_SPEED_STANDARD" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + register "bckup_sw_mode" = "BACKUP_SW_LEVEL" + register "cap_charge" = "CHARGE_OFF" + device i2c 0x52 on end # RTC RV3028-C7 + end + end + device pci 15.2 on # I2C2 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end + device pci 15.3 on end # I2C3 + + device pci 16.0 hidden end # Management Engine Interface 1 + + device pci 19.0 on end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 on end # SD + + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1d.0 off end # Intel PSE IPC (local host to PSE) + device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 + # Enable external Marvell PHY 88E1512 + chip drivers/net/phy/m88e1512 + register "configure_leds" = "true" + # LED[0]: On - 1000 Mbps Link, Off - Else + register "led_0_ctrl" = "7" + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" + register "downshift_cnt" = "2" + register "force_mos" = "true" + register "pmos_val" = "0xF" + register "nmos_val" = "0xA" + device mdio 0 on # PHY address + ops m88e1512_ops + end + end + end + device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 + # Enable external Marvell PHY 88E1512 + chip drivers/net/phy/m88e1512 + register "configure_leds" = "true" + # LED[0]: On - 1000 Mbps Link, Off - Else + register "led_0_ctrl" = "7" + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" + register "downshift_cnt" = "2" + register "force_mos" = "true" + register "pmos_val" = "0xF" + register "nmos_val" = "0xA" + device mdio 1 on # PHY address + ops m88e1512_ops + end + end + end + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + device pci 1e.4 on # PCH Time-Sensitive Networking GbE + # Enable external Marvell PHY 88E1512 + chip drivers/net/phy/m88e1512 + register "configure_leds" = "true" + # LED[0]: On - 1000 Mbps Link, Off - Else + register "led_0_ctrl" = "7" + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" + register "downshift_cnt" = "2" + device mdio 1 on # PHY address + ops m88e1512_ops + end + end + end + + device pci 1f.0 on # eSPI Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI (flash & TPM) + end +end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c new file mode 100644 index 0000000..20a89c6 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* Community 0 - GpioGroup GPP_B */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ + PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ + PAD_NC(GPP_B4, NONE), /* Not connected */ + PAD_NC(GPP_B9, NONE), /* Not connected */ + PAD_NC(GPP_B10, NONE), /* Not connected */ + PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ + PAD_NC(GPP_B14, NONE), /* Not connected */ + PAD_NC(GPP_B15, NONE), /* Not connected */ + PAD_NC(GPP_B18, NONE), /* Not connected */ + PAD_NC(GPP_B19, NONE), /* Not connected */ + PAD_NC(GPP_B23, NONE), /* Not connected */ + + /* Community 0 - GpioGroup GPP_T */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */ + + /* Community 0 - GpioGroup GPP_G */ + PAD_NC(GPP_G8, NONE), /* Not connected */ + PAD_NC(GPP_G9, NONE), /* Not connected */ + PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ + + /* Community 1 - GpioGroup GPP_V */ + PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */ + + /* Community 1 - GpioGroup GPP_H */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* PSE_GBE1_INT */ + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* PSE_GBE1_RST_N */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* PCIE_CLKREQ4_N */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCIE_CLKREQ5_N */ + + /* Community 1 - GpioGroup GPP_D */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* PCIE_CLKREQ3_N */ + + /* Community 1 - GpioGroup GPP_U */ + PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), /* GBE_INT */ + PAD_CFG_GPO(GPP_U1, 1, DEEP), /* GBE_RST_N */ + PAD_NC(GPP_U12, NONE), /* Not connected */ + PAD_NC(GPP_U13, NONE), /* Not connected */ + PAD_NC(GPP_U16, NONE), /* Not connected */ + PAD_NC(GPP_U17, NONE), /* Not connected */ + PAD_NC(GPP_U18, NONE), /* Not connected */ + + /* Community 2 - GpioGroup DSW */ + PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), /* ACPRESENT */ + PAD_NC(GPD9, NONE), /* Not connected */ + PAD_NC(GPD11, NONE), /* Not connected */ + + /* Community 3 - GpioGroup GPP_S */ + PAD_NC(GPP_S0, NONE), /* Not connected */ + PAD_NC(GPP_S1, NONE), /* Not connected */ + + /* Community 3 - GpioGroup GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCTL */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ + + /* Community 4 - GpioGroup GPP_C */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */ + PAD_NC(GPP_C8, NONE), /* Not connected */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ + + /* Community 4 - GpioGroup GPP_F */ + PAD_NC(GPP_F1, NONE), /* Not connected */ + PAD_NC(GPP_F3, NONE), /* Not connected */ + PAD_NC(GPP_F8, NONE), /* Not connected */ + PAD_NC(GPP_F11, NONE), /* Not connected */ + PAD_NC(GPP_F12, NONE), /* Not connected */ + PAD_NC(GPP_F13, NONE), /* Not connected */ + PAD_NC(GPP_F14, NONE), /* Not connected */ + PAD_NC(GPP_F15, NONE), /* Not connected */ + PAD_NC(GPP_F16, NONE), /* Not connected */ + PAD_NC(GPP_F17, NONE), /* Not connected */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* LED_BIOS_DONE */ + + /* Community 4 - GpioGroup GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */ + PAD_NC(GPP_E15, NONE), /* Not connected */ + PAD_NC(GPP_E16, NONE), /* Not connected */ + PAD_NC(GPP_E18, NONE), /* Not connected */ + PAD_NC(GPP_E19, NONE), /* Not connected */ + PAD_NC(GPP_E23, NONE), /* Not connected */ + + /* Community 5 - GpioGroup GPP_R */ + PAD_NC(GPP_R1, NONE), /* Not connected */ + PAD_NC(GPP_R3, NONE), /* Not connected */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c new file mode 100644 index 0000000..1121399 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <device/pci_ids.h> +#include <gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> + +#define HOSTCTRL2 0x3E +#define HOSTCTRL2_PRESET (1 << 15) +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 +#define SD_CAP_BYP_SDR50 (1 << 13) +#define SD_CAP_BYP_SDR104 (1 << 14) +#define SD_CAP_BYP_DDR50 (1 << 15) + +void variant_mainboard_final(void) +{ + struct device *dev; + + /* PIR8 register mapping for PCIe root ports + INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ + pcr_write16(PID_ITSS, 0x3150, 0x1032); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to + layout limitations. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + uint32_t reg; + uint16_t reg16; + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); + /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ + reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); + reg |= SD_CAP_BYP_DDR50; + write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + /* Use preset driver strength from preset value registers. */ + reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); + reg16 |= HOSTCTRL2_PRESET; + write16(res2mmio(res, HOSTCTRL2, 0), reg16); + } +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(GPP_F20, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c new file mode 100644 index 0000000..7b7dad1 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &mc_ehl_lpddr4x_memcfg_cfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Gerrit-Change-Number: 74935 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [RFC] drivers/option: Add option list in cbtable
by Angel Pons (Code Review) 03 May '23

03 May '23

Attention is currently required from: Sean Rhodes, Nico Huber, Benjamin Doron, Maximilian Brune, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74121 ) Change subject: [RFC] drivers/option: Add option list in cbtable ...................................................................... Patch Set 4: (1 comment) File src/drivers/option/cfr.h: https://review.coreboot.org/c/coreboot/+/74121/comment/86c89424_917a1c0e PS4, Line 201: CFR_FORM Does not match the code -- To view, visit https://review.coreboot.org/c/coreboot/+/74121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 12:08:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/variants/baseboard/rex: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74754 ) Change subject: mb/google/rex/variants/baseboard/rex: Add CPU power limit values ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/ramstage.c: https://review.coreboot.org/c/coreboot/+/74754/comment/bed9b3c5_bcdd4527 PS3, Line 8: pl1_min > nit: would you please mind to write the units like u did for TDP Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Gerrit-Change-Number: 74754 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 03 May 2023 12:04:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/variants/baseboard/rex: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sumeet R Pawnikar. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74754 to look at the new patch set (#5). Change subject: mb/google/rex/variants/baseboard/rex: Add CPU power limit values ...................................................................... mb/google/rex/variants/baseboard/rex: Add CPU power limit values Add CPU power limit values for rex baseboard BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc A src/mainboard/google/rex/variants/baseboard/rex/ramstage.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/74754/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Gerrit-Change-Number: 74754 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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