Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P.
Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72785 )
Change subject: mb/intel/mtlrvp: Describe TCSS USB ports
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/72785/comment/60612acc_f90be76a
PS2, Line 51: register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
> Tried something like this, […]
UPC_TYPE_HUB is fine outside, but register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" should be a port.
--
To view, visit https://review.coreboot.org/c/coreboot/+/72785
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0
Gerrit-Change-Number: 72785
Gerrit-PatchSet: 3
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 06:19:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com>
Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P.
Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72785 )
Change subject: mb/intel/mtlrvp: Describe TCSS USB ports
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/72785/comment/a084a363_4163443f
PS2, Line 51: register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
> why here? should belong the to each port.
Tried something like this,
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/adlrvp…
Should this be still moved under each port?
--
To view, visit https://review.coreboot.org/c/coreboot/+/72785
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0
Gerrit-Change-Number: 72785
Gerrit-PatchSet: 3
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 06:17:45 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: Jamie Ryu, Harsha B R, Usha P.
Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72777
to look at the new patch set (#4).
Change subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
......................................................................
mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
This patch enables PCIe port for WWAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module
gets enumerated with cbmem -c.
\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/72777/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/72777
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Gerrit-Change-Number: 72777
Gerrit-PatchSet: 4
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Subrata Banik, Jérémy Compostella, Sumeet R Pawnikar, Nick Vaccaro.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71692 )
Change subject: mb/google/brya/var/skolas: update dptf thermal settings
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
> We will check and submit separate patch if required.
Sumeet please push the Brya0 patches also, we try to keep skolas/Brya0 at the same level. The only diff is Brya0 has ADL microcode's included so that it can boot on RPL and ADL.
PS5:
Thx Sumeet
--
To view, visit https://review.coreboot.org/c/coreboot/+/71692
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
Gerrit-Change-Number: 71692
Gerrit-PatchSet: 5
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 04:54:03 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com>
Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-MessageType: comment
Attention is currently required from: Bora Guvendik, Subrata Banik, Jérémy Compostella, Nick Vaccaro.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71692 )
Change subject: mb/google/brya/var/skolas: update dptf thermal settings
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Don't we need the same changes for Brya0?
We will check and submit separate patch if required.
--
To view, visit https://review.coreboot.org/c/coreboot/+/71692
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
Gerrit-Change-Number: 71692
Gerrit-PatchSet: 5
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 04:39:56 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-MessageType: comment
Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72747 )
Change subject: soc/mediatek: Add support for regulator VM18
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72747/comment/4de74e3a_f3692b63
PS1, Line 9: Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0.
> To provide power to mipi panel BOE_TV110C9M_LL0, add support for regulator VM18.
mipi -> MIPI
Patchset:
PS2:
> src/mainboard/google/corsola/regulator. […]
We may change the `regulator_id` array to a function similar to Geralt's `get_mt6359p_regulator_id()`.
--
To view, visit https://review.coreboot.org/c/coreboot/+/72747
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799
Gerrit-Change-Number: 72747
Gerrit-PatchSet: 2
Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 04:16:20 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-MessageType: comment
Attention is currently required from: Harsha B R, Usha P.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72778 )
Change subject: mb/intel/mtlrvp: Enable PCIe port 8 for WLAN
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/72778
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74
Gerrit-Change-Number: 72778
Gerrit-PatchSet: 3
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 04:13:27 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Jamie Ryu, Harsha B R, Usha P.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72777 )
Change subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72777/comment/a2681cba_2de97ebb
PS3, Line 17: \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)
Do you see the PCIE device in the lspci output?
--
To view, visit https://review.coreboot.org/c/coreboot/+/72777
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Gerrit-Change-Number: 72777
Gerrit-PatchSet: 3
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 04:13:14 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P.
Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72787 )
Change subject: mb/intel/mtlrvp: Add ACPI configuration for USB2/3 ports
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/72787
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie150247661322e3944be15dc70f66033266d8aac
Gerrit-Change-Number: 72787
Gerrit-PatchSet: 3
Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Usha P <usha.p(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Usha P <usha.p(a)intel.com>
Gerrit-Comment-Date: Mon, 06 Feb 2023 03:58:37 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment