coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[L] Change in coreboot[master]: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
by David Hendricks (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Subrata Banik, Simon Chou, TimLiu-SMCI, Jonathan Zhang, Johnny Lin, Paul Menzel, Christian Walter, Angel Pons, Jian-Ming Wang, Arthur Heymans, Shuming Chu (Shuming), Elyes Haouas. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71945 ) Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/71945/comment/21d9e469_1e09d9ae PS8, Line 187: #define GPP_E20 132 : #define GPP_E21 133 : #define GPP_E22 134 : #define GPP_E23 135 > These fields are not defined in EDS but can be found while using Cscript. […] I see them now - they are mentioned in the GPI_NMI_EN_GPP_E_0 register, but not in certain other registers like other GPIOs in this community. Thanks for double-checking! https://review.coreboot.org/c/coreboot/+/71945/comment/8f667833_2296af35 PS8, Line 192: GPP_E23 > Although GPP_E23 is not defined in EDS but it does exist, should we change this to GPP_E19? No, let's keep this as-is with GPP_E23 since it exists as you say. -- To view, visit https://review.coreboot.org/c/coreboot/+/71945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Gerrit-Change-Number: 71945 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 06 Feb 2023 07:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/{common, meteorlake}: Add support for new MCH
by Sridhar Siricilla (Code Review) 06 Feb '23

06 Feb '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72835 ) Change subject: soc/intel/{common, meteorlake}: Add support for new MCH ...................................................................... soc/intel/{common, meteorlake}: Add support for new MCH The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/meteorlake/bootblock/report_platform.c M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/systemagent.c 5 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72835/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dbc1706..6c32620 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4106,6 +4106,7 @@ #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 +#define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index aeeff12..174d511 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -341,6 +341,7 @@ PCI_DID_INTEL_MTL_P_ID_2, PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, + PCI_DID_INTEL_MTL_P_ID_5, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 982a0c5..a5d32f3 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -30,6 +30,7 @@ { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, + { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, }; static struct { diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 4e95321..9403980 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -23,6 +23,7 @@ MTL_P_POWER_LIMITS_2, MTL_P_POWER_LIMITS_3, MTL_P_POWER_LIMITS_4, + MTL_P_POWER_LIMITS_5, MTL_POWER_LIMITS_COUNT }; diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 81e4bed..c133966 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -181,6 +181,9 @@ case PCI_DID_INTEL_MTL_P_ID_4: soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4]; break; + case PCI_DID_INTEL_MTL_P_ID_5: + soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_5]; + break; default: printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", sa_pci_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/72835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Gerrit-Change-Number: 72835 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: tree: drop repeated words
by Erik van den Bogaert (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Martin L Roth, Frans Hendriks, Patrick Rudolph, Jakub Czapiga, Christian Walter, Angel Pons, Julius Werner, Lean Sheng Tan, Alexander Couzens, Evgeny Zinoviev, Alexander Goncharov. Erik van den Bogaert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72795 ) Change subject: tree: drop repeated words ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Gerrit-Change-Number: 72795 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Mon, 06 Feb 2023 07:30:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/brya: Create aurash variant
by Zoey Wu (Code Review) 06 Feb '23

06 Feb '23

Zoey Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72834 ) Change subject: mb/google/brya: Create aurash variant ...................................................................... mb/google/brya: Create aurash variant Create the aurash variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263691099 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AURASH Change-Id: I4c68355f55345dc2b31819fa7bdba2e20f6079ed Signed-off-by: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/Kconfig.name.rej A src/mainboard/google/brya/variants/aurash/include/variant/ec.h A src/mainboard/google/brya/variants/aurash/include/variant/gpio.h A src/mainboard/google/brya/variants/aurash/overridetree.cb 5 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/72834/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index dad9821..7e01525 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -225,6 +225,7 @@ default "Gladios" if BOARD_GOOGLE_GLADIOS default "Marasov" if BOARD_GOOGLE_MARASOV default "Omnigul" if BOARD_GOOGLE_OMNIGUL + default "Aurash" if BOARD_GOOGLE_AURASH config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -267,6 +268,7 @@ default "gladios" if BOARD_GOOGLE_GLADIOS default "marasov" if BOARD_GOOGLE_MARASOV default "omnigul" if BOARD_GOOGLE_OMNIGUL + default "aurash" if BOARD_GOOGLE_AURASH config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name.rej b/src/mainboard/google/brya/Kconfig.name.rej new file mode 100644 index 0000000..2ef71b3 --- /dev/null +++ b/src/mainboard/google/brya/Kconfig.name.rej @@ -0,0 +1,9 @@ +diff a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name (rejected hunks) +@@ -331,3 +331,7 @@ config BOARD_GOOGLE_OMNIGUL + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ++ ++config BOARD_GOOGLE_AURASH ++ bool "-> Aurash" ++ select BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/aurash/include/variant/ec.h b/src/mainboard/google/brya/variants/aurash/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/aurash/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/aurash/include/variant/gpio.h b/src/mainboard/google/brya/variants/aurash/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/aurash/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/72834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c68355f55345dc2b31819fa7bdba2e20f6079ed Gerrit-Change-Number: 72834 Gerrit-PatchSet: 1 Gerrit-Owner: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point"
by Shon Wang (Code Review) 06 Feb '23

06 Feb '23

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72833 ) Change subject: Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point" ...................................................................... Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point" This reverts commit e30695dbe196ea42864ad03af799706eaae11f02. for meet thermal criteria, modify PS1/PS2 cutoff to default value BUG=b:229803757 Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2 Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/72833/1 diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 3f11502..8751350 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -550,12 +550,4 @@ end end end - - # VR Settings - register "domain_vr_config[VR_DOMAIN_IA]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(13), - .psi2threshold = VR_CFG_AMP(7), - }" - end -- To view, visit https://review.coreboot.org/c/coreboot/+/72833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2 Gerrit-Change-Number: 72833 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Describe TCSS USB ports
by Eric Lai (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72785 ) Change subject: mb/intel/mtlrvp: Describe TCSS USB ports ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Gerrit-Change-Number: 72785 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 06:55:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Describe TCSS USB ports
by Harsha B R (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72785 ) Change subject: mb/intel/mtlrvp: Describe TCSS USB ports ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/72785/comment/283a4b86_4a8ae83b PS2, Line 51: register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" > UPC_TYPE_HUB is fine outside, but register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" should be a port. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/72785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Gerrit-Change-Number: 72785 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 06:51:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Describe TCSS USB ports
by Harsha B R (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72785 to look at the new patch set (#4). Change subject: mb/intel/mtlrvp: Describe TCSS USB ports ...................................................................... mb/intel/mtlrvp: Describe TCSS USB ports This patch describes the TCSS USB ports for mtlrvp as per schematics. This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below, tcss_usb3_port1: USB3 Type-C Port C0 tcss_usb3_port2: USB3 Type-C Port C1 tcss_usb3_port3: USB3 Type-C Port C2 tcss_usb3_port4: USB3 Type-C Port C3 BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C ports as part of cbmem -c. Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 54 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/72785/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Gerrit-Change-Number: 72785 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
by Eric Lai (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72777 ) Change subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Gerrit-Change-Number: 72777 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 06:46:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
by Harsha B R (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72777 ) Change subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72777/comment/b1e84af9_bab75ba9 PS3, Line 17: \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) > Do you see the PCIE device in the lspci output? yes, it appears as below, 00:1c.6 PCI bridge: Intel Corporation Device 7e3e (rev 01) Without this Cl there is no enumeration. File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/72777/comment/393c4a73_1dcb1b88 PS3, Line 57: | > space Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Gerrit-Change-Number: 72777 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 06:39:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023