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Change subject: soc/intel/rtd3: Hook up supported states to Kconfig
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72765/comment/a9c76c61_5f16cab0
PS3, Line 12: When D3COLD_SUPPORT is enabled, return `3` (D3Hot).
> not enabled?
Thanks!
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Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72765
to look at the new patch set (#4).
Change subject: soc/intel/rtd3: Hook up supported states to Kconfig
......................................................................
soc/intel/rtd3: Hook up supported states to Kconfig
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it
is not, it will break S3 exit.
When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).
This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 22 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/72765/4
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72765 )
Change subject: soc/intel/rtd3: Hook up supported states to Kconfig
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72765/comment/8a58d713_974b79c1
PS3, Line 12: When D3COLD_SUPPORT is enabled, return `3` (D3Hot).
not enabled?
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Change subject: soc/intel/alderlake: Remove unused S0IX variable
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
......................................................................
Patch Set 11:
(9 comments)
File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/71945/comment/0a193515_ab34702b
PS8, Line 204: #define GPPC_H8 144
: #define GPPC_H9 145
: #define GPPC_H10 146
: #define GPPC_H11 147
: #define GPPC_H12 148
: #define GPPC_H13 149
: #define GPPC_H14 150
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 20, the offset assigned for GPPC_H7 and GPPC_H15.
https://review.coreboot.org/c/coreboot/+/71945/comment/ac335c89_23b8fe67
PS8, Line 227: #define GPP_J9 165
: #define GPP_J10 166
: #define GPP_J11 167
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 21, the offset assigned for GPPC_J8 and GPPC_J12.
https://review.coreboot.org/c/coreboot/+/71945/comment/9eb582ba_9a01535f
PS8, Line 234: #define GPP_J16 172
: #define GPP_J17 173
> Tim, could you check this?
GPP_J15 is the last pad configuration in EDS for GPIO community 4. GPP_J16 and GPP_J17 are defined as unrouted GPIOs in #606161 page 1692.
https://review.coreboot.org/c/coreboot/+/71945/comment/9d8b5432_08dff3a7
PS8, Line 244: define GPP_I3 183
: #define GPP_I4 184
: #define GPP_I5 185
: #define GPP_I6 186
: #define GPP_I7 187
: #define GPP_I8 188
: #define GPP_I9 189
: #define GPP_I10 190
: #define GPP_I11 191
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 23, the offset assigned for GPPC_I12.
https://review.coreboot.org/c/coreboot/+/71945/comment/f96f77d7_045cc315
PS8, Line 259: #define GPP_I18 198
: #define GPP_I19 199
: #define GPP_I20 200
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 23, the offset assigned for GPPC_I17 and GPPC_I21.
https://review.coreboot.org/c/coreboot/+/71945/comment/cd3eba78_6efeb631
PS8, Line 276: #define GPP_L9 213
: #define GPP_L10 214
: #define GPP_L11 215
: #define GPP_L12 216
: #define GPP_L13 217
: #define GPP_L14 218
: #define GPP_L15 219
: #define GPP_L16 220
: #define GPP_L17 221
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. I think the reserved entries are correct based on the calculation of offset of PAD_CFG_DW0_GPP_L_8 and PAD_CFG_DW0_CPP_M_0.
Please check #606161 page 24, the offset assigned for GPPC_L8 and GPPC_M0.
https://review.coreboot.org/c/coreboot/+/71945/comment/bff7fea9_b7cecb6d
PS8, Line 296: #define GPP_M9 231
: #define GPP_M10 232
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 24, the offset assigned for GPPC_M8 and GPPC_M11.
https://review.coreboot.org/c/coreboot/+/71945/comment/f883a01f_ec001f45
PS8, Line 300: #define GPP_M13 235
: #define GPP_M14 236
> Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept.
Please check #606161 page 25, the offset assigned for GPPC_M12 and GPPC_M15.
https://review.coreboot.org/c/coreboot/+/71945/comment/3d54e3f4_79f66077
PS8, Line 312: #define GPP_N5 245
: #define GPP_N6 246
: #define GPP_N7 247
: #define GPP_N8 248
: #define GPP_N9 249
: #define GPP_N10 250
: #define GPP_N11 251
: #define GPP_N12 252
: #define GPP_N13 253
: #define GPP_N14 254
: #define GPP_N15 255
: #define GPP_N16 256
: #define GPP_N17 257
> Tim, could you check this?
GPP_N4 is the last pad configuration in EDS for GPIO community 5. However, GPP_N5 to GPP_N17 were defined in "Unrouted GPIOs".
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Change subject: mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0
......................................................................
Patch Set 4:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72749/comment/9fa6b520_0d067385
PS1, Line 7: power on
> power-on
Done
https://review.coreboot.org/c/coreboot/+/72749/comment/9611e5ae_c559955a
PS1, Line 9: Add power sequence to power on BOE_TV110C9M_LL0 on Geralt proto board.
> For Geralt, we use BOE_TV110C9M_LL0 as mipi firmware display, so […]
Done
https://review.coreboot.org/c/coreboot/+/72749/comment/d663e651_7bdb240a
PS1, Line 12: on Geralt proto
: board
> on Geralt.
Done
File src/mainboard/google/geralt/panel_geralt.c:
https://review.coreboot.org/c/coreboot/+/72749/comment/35ab73e8_39a0bd99
PS1, Line 22: static int mipi_panel_reg_mask (u8 addr, u8 val, u8 mask)
> move to panel.c.
Done
https://review.coreboot.org/c/coreboot/+/72749/comment/a8aa8f3e_87750746
PS1, Line 26: if (i2c_read_field(MIPI_PANEL_I2C, MIPI_PANEL_SLAVE, addr, &msg, 0xFF, 0))
: printk(BIOS_ERR, "Rex: failed to read i2c: %d\n", addr);
> ` […]
Done
https://review.coreboot.org/c/coreboot/+/72749/comment/30ca66fb_3d16d88d
PS1, Line 66: ret = mipi_panel_reg_mask(0x00, 0x11, 0x1F);
:
: /* Set AVEE = -5.7V */
: ret = mipi_panel_reg_mask(0x01, 0x11, 0x1F);
:
: /* Disable AVDD & AVEE discharge when power on*/
: ret = mipi_panel_reg_mask(0x03, 0x30, 0xFF);
> do some error handling
Done
File src/mainboard/google/geralt/panel_geralt.c:
https://review.coreboot.org/c/coreboot/+/72749/comment/433f58aa_c21823e6
PS3, Line 51: mt6359p_init
> mt6359 has been initialized in romstage. Can we just initialize it only once? […]
Done
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Change subject: mb/google/geralt: Add API to control VM18 in regulator.c
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72748/comment/317613af_b7e90460
PS1, Line 7: Add regulator VM18 support to supply power for BOE_TV110C9M_LL0
> Add API to control VM18 in regulator. […]
Done
https://review.coreboot.org/c/coreboot/+/72748/comment/a8ab95a0_c17ed4ad
PS1, Line 12: on Geralt proto
: board
> on Geralt.
Done
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Change subject: soc/mediatek: Add support for regulator VM18
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72747/comment/f6d793f2_360a4a7d
PS1, Line 7: Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0
> soc/mediatek: Add support for regulator VM18
Done
https://review.coreboot.org/c/coreboot/+/72747/comment/dd64c4ef_677c1ce7
PS1, Line 9: Implement VM18 enable interface to supply power for BOE_TV110C9M_LL0.
> mipi -> MIPI
Done
https://review.coreboot.org/c/coreboot/+/72747/comment/69435144_d1fff6b7
PS1, Line 12: test firmware display pass for BOE_TV110C9M_LL0 on Geralt proto
: board
> test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Done
Patchset:
PS2:
> We may change the `regulator_id` array to a function similar to Geralt's `get_mt6359p_regulator_id() […]
Done
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