coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[S] Change in coreboot[master]: soc/amd/phoenix: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72186 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/phoenix: remove LIDS field from global NVS ...................................................................... soc/amd/phoenix: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Phoenix SoC, remove it form the global NVS. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/72186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/phoenix/acpi/globalnvs.asl M src/soc/amd/phoenix/include/soc/nvs.h 2 files changed, 22 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/phoenix/acpi/globalnvs.asl b/src/soc/amd/phoenix/acpi/globalnvs.asl index 251c331..f5a6aa5 100644 --- a/src/soc/amd/phoenix/acpi/globalnvs.asl +++ b/src/soc/amd/phoenix/acpi/globalnvs.asl @@ -8,8 +8,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source } diff --git a/src/soc/amd/phoenix/include/soc/nvs.h b/src/soc/amd/phoenix/include/soc/nvs.h index 74b0d2d..35f27aa 100644 --- a/src/soc/amd/phoenix/include/soc/nvs.h +++ b/src/soc/amd/phoenix/include/soc/nvs.h @@ -13,10 +13,9 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ }; #endif /* AMD_PHOENIX_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa Gerrit-Change-Number: 72186 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/phoenix: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72186 to look at the new patch set (#2). Change subject: soc/amd/phoenix: remove LIDS field from global NVS ...................................................................... soc/amd/phoenix: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Phoenix SoC, remove it form the global NVS. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa --- M src/soc/amd/phoenix/acpi/globalnvs.asl M src/soc/amd/phoenix/include/soc/nvs.h 2 files changed, 19 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/72186/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa Gerrit-Change-Number: 72186 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72185 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/mendocino: remove LIDS field from global NVS ...................................................................... soc/amd/mendocino: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/skyrim/dsdt.asl M src/soc/amd/mendocino/acpi/globalnvs.asl M src/soc/amd/mendocino/include/soc/nvs.h 3 files changed, 27 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/dsdt.asl b/src/mainboard/google/skyrim/dsdt.asl index 7293683..1a41165 100644 --- a/src/mainboard/google/skyrim/dsdt.asl +++ b/src/mainboard/google/skyrim/dsdt.asl @@ -13,6 +13,9 @@ ) { #include <acpi/dsdt_top.asl> + + Name(LIDS, 0) + #include <soc.asl> #if CONFIG(FEATURE_DYNAMIC_DPTC) #include <variant/acpi/dtts.asl> diff --git a/src/soc/amd/mendocino/acpi/globalnvs.asl b/src/soc/amd/mendocino/acpi/globalnvs.asl index 7aa5de3..4161e5f 100644 --- a/src/soc/amd/mendocino/acpi/globalnvs.asl +++ b/src/soc/amd/mendocino/acpi/globalnvs.asl @@ -8,8 +8,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source } diff --git a/src/soc/amd/mendocino/include/soc/nvs.h b/src/soc/amd/mendocino/include/soc/nvs.h index 085de01..928a310 100644 --- a/src/soc/amd/mendocino/include/soc/nvs.h +++ b/src/soc/amd/mendocino/include/soc/nvs.h @@ -13,10 +13,9 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ }; #endif /* AMD_MENDOCINO_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Gerrit-Change-Number: 72185 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72185 to look at the new patch set (#2). Change subject: soc/amd/mendocino: remove LIDS field from global NVS ...................................................................... soc/amd/mendocino: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d --- M src/mainboard/google/skyrim/dsdt.asl M src/soc/amd/mendocino/acpi/globalnvs.asl M src/soc/amd/mendocino/include/soc/nvs.h 3 files changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/72185/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Gerrit-Change-Number: 72185 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/cezanne: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72184 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/cezanne: remove LIDS field from global NVS ...................................................................... soc/amd/cezanne: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/dsdt.asl M src/soc/amd/cezanne/acpi/globalnvs.asl M src/soc/amd/cezanne/include/soc/nvs.h 3 files changed, 27 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl index 6c208cf..782bd9d 100644 --- a/src/mainboard/google/guybrush/dsdt.asl +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -13,6 +13,9 @@ ) { #include <acpi/dsdt_top.asl> + + Name(LIDS, 0) + #include <soc.asl> /* ChromeOS Embedded Controller */ diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl index bccce09..f4a6c5f 100644 --- a/src/soc/amd/cezanne/acpi/globalnvs.asl +++ b/src/soc/amd/cezanne/acpi/globalnvs.asl @@ -8,8 +8,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source } diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h index d990f45..d1a8e30 100644 --- a/src/soc/amd/cezanne/include/soc/nvs.h +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -13,10 +13,9 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ }; #endif /* AMD_CEZANNE_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Gerrit-Change-Number: 72184 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/cezanne: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72184 to look at the new patch set (#2). Change subject: soc/amd/cezanne: remove LIDS field from global NVS ...................................................................... soc/amd/cezanne: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc --- M src/mainboard/google/guybrush/dsdt.asl M src/soc/amd/cezanne/acpi/globalnvs.asl M src/soc/amd/cezanne/include/soc/nvs.h 3 files changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/72184/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Gerrit-Change-Number: 72184 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/picasso: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72183 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/picasso: remove LIDS field from global NVS ...................................................................... soc/amd/picasso: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h 3 files changed, 32 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 62520b9..d715cde 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -17,6 +17,8 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> + Name(LIDS, 0) + /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index f616361..2d24b88 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -9,11 +9,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source - TMPS, 8, // 0x15 - Temperature Sensor ID - TCRT, 8, // 0x16 - Critical Threshold - TPSV, 8, // 0x17 - Passive Threshold + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source + TMPS, 8, // 0x14 - Temperature Sensor ID + TCRT, 8, // 0x15 - Critical Threshold + TPSV, 8, // 0x16 - Passive Threshold } diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index aef4a97..c5821bb 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -14,13 +14,12 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ - uint8_t tmps; /* 0x15 - Temperature Sensor ID */ - uint8_t tcrt; /* 0x16 - Critical Threshold */ - uint8_t tpsv; /* 0x17 - Passive Threshold */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ + uint8_t tmps; /* 0x14 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x15 - Critical Threshold */ + uint8_t tpsv; /* 0x16 - Passive Threshold */ }; #endif /* AMD_PICASSO_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Gerrit-Change-Number: 72183 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/picasso: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72183 to look at the new patch set (#2). Change subject: soc/amd/picasso: remove LIDS field from global NVS ...................................................................... soc/amd/picasso: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 --- M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h 3 files changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/72183/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Gerrit-Change-Number: 72183 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/amd/stoneyridge: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72182 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/stoneyridge: remove LIDS field from global NVS ...................................................................... soc/amd/stoneyridge: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/kahlee/dsdt.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 3 files changed, 37 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 17acb27..8a88848 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -16,6 +16,8 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> + Name(LIDS, 0) + /* Globals for the platform */ #include <variant/acpi/mainboard.asl> diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 703e16f..7f3fe1b 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -9,13 +9,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source - TMPS, 8, // 0x15 - Temperature Sensor ID - TCRT, 8, // 0x16 - Critical Threshold - TPSV, 8, // 0x17 - Passive Threshold + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source + TMPS, 8, // 0x14 - Temperature Sensor ID + TCRT, 8, // 0x15 - Critical Threshold + TPSV, 8, // 0x16 - Passive Threshold Offset (0x20), // 0x20 - AOAC Device Enables , 5, IC0E, 1, // I2C0, 5 diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index d296458..eaaf1bd 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -14,14 +14,13 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ - uint8_t tmps; /* 0x15 - Temperature Sensor ID */ - uint8_t tcrt; /* 0x16 - Critical Threshold */ - uint8_t tpsv; /* 0x17 - Passive Threshold */ - uint8_t pad1[8]; + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ + uint8_t tmps; /* 0x14 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x15 - Critical Threshold */ + uint8_t tpsv; /* 0x16 - Passive Threshold */ + uint8_t pad1[9]; aoac_devs_t aoac; /* 0x20 - AOAC device enables */ uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */ uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Gerrit-Change-Number: 72182 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/stoneyridge: remove LIDS field from global NVS
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Patrick Georgi, Jason Nien, Matt DeVillier, Martin Roth, Felix Held. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Matt DeVillier, Matt DeVillier, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72182 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge: remove LIDS field from global NVS ...................................................................... soc/amd/stoneyridge: remove LIDS field from global NVS Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f --- M src/mainboard/google/kahlee/dsdt.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 3 files changed, 33 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/72182/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Gerrit-Change-Number: 72182 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023