coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek: Add support for regulator VM18
by Paul Menzel (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72747 ) Change subject: soc/mediatek: Add support for regulator VM18 ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/common/mt6359p.c: https://review.coreboot.org/c/coreboot/+/72747/comment/4d7e0cef_674300bc PS3, Line 329: !!enable Enable is already a boolean, so the !! is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/72747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799 Gerrit-Change-Number: 72747 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 15:43:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model
by Paul Menzel (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72843 ) Change subject: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4 Gerrit-Change-Number: 72843 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Feb 2023 15:42:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Use common codeflow for MP init
by Dinesh Gehlot (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Arthur Heymans, Werner Zeh, Tim Chu. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72604 ) Change subject: soc/intel: Use common codeflow for MP init ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: CPU frequency seems to be dropping with the changes. On ToT bin it was ~1200MHz but it drops to ~400MHz for few cases with changes for rex. Steps to reproduce: 1. Check CPU information from AP console. 2. Compare all occurrence of key word "CPU MHz" ``` localhost ~ cat /proc/cpuinfo ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/72604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Gerrit-Change-Number: 72604 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 15:39:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne: remove LIDS field from global NVS
by 9elements QA (Code Review) 06 Feb '23

06 Feb '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72184 ) Change subject: soc/amd/cezanne: remove LIDS field from global NVS ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149767 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149765 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/149764 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/149763 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/149762 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149761 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/149760 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/149759 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/149758 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/149757 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/149756 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/149755 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149754 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/149753 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/149752 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/149751 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/72184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Gerrit-Change-Number: 72184 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 15:04:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz
by Nick Vaccaro (Code Review) 06 Feb '23

06 Feb '23

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68906 ) Change subject: mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: AlanKY, is this change not needed for brya0 as well? Or is the timing for skolas slightly different due to skolas having RPL and brya0 having ADL? -- To view, visit https://review.coreboot.org/c/coreboot/+/68906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Gerrit-Change-Number: 68906 Gerrit-PatchSet: 2 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:50:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model
by Felix Held (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72843 ) Change subject: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/phoenix/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/72843/comment/2b5f4c5c_36b4def7 PS1, Line 6: #define PHOENIX2_A0_CPUID 0x00a70f80 > Phoenix is 0x00a70f00, can be added here too i have a separate patch for that, but i'm waiting with uploading that one until i'm done with a tree-wide patch that allows handling multiple stepping ids with one entry. there is more than one phoenix stepping and that caused me to look into writing a larger scale patch before that -- To view, visit https://review.coreboot.org/c/coreboot/+/72843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4 Gerrit-Change-Number: 72843 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Nick Vaccaro (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Ron Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 6: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 6 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:26:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Nick Vaccaro (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Ron Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 6: -Code-Review (1 comment) Patchset: PS6: Why was this change not made for brya0? -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 6 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Calling mt6359p_init() only once in ramstage
by Paul Menzel (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72839 ) Change subject: mb/google/geralt: Calling mt6359p_init() only once in ramstage ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72839/comment/223f69e1_b71778f8 PS1, Line 7: Calling (Please use imperative mood: Call instead of Calling) Maybe: > Init MT6359P only once in ramstage https://review.coreboot.org/c/coreboot/+/72839/comment/3526f8ea_55fbf734 PS1, Line 10: mt6359 mt6359p? https://review.coreboot.org/c/coreboot/+/72839/comment/59ef73ce_b87af19b PS1, Line 12: What user visible problem does multiple initialization cause? -- To view, visit https://review.coreboot.org/c/coreboot/+/72839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Gerrit-Change-Number: 72839 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Nick Vaccaro (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Ron Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 6 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 14:19:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023