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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72421 )
Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logic
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/72421/comment/b9fed257_e27a0b38
PS2, Line 264: /* for enable pin:
This is clearly not a one liner comment and therefore the syntax you used is incorrect. I also think that:
1. The explanation could use a little bit more text
2. This should actually be the function comment instead of an in-function comment.
Here is what I suggest.
```
/*
* Depending on the board configuration we use either the "enable" or the
* "reset" pin to detect the status of the device. The logic for each pin is
* detailed below.
*
* 1. For the "enable" pin:
* | polarity | tx value | get_tx_gpio() | State |
* |-------------+----------+---------------+-------|
* | active high | 0 | 0 | 0 |
* | active high | 1 | 1(active) | 1 |
* | active low | 0 | 1(active) | 1 |
* | active low | 1 | 0 | 0 |
*
* 2. For the the "reset" pin:
* | polarity | tx value | get_tx_gpio() | State |
* |-------------+----------+---------------+-------|
* | active high | 0 | 0 | 1 |
* | active high | 1 | 1(active) | 0 |
* | active low | 0 | 1(active) | 0 |
* | active low | 1 | 0 | 1 |
*/
```
https://review.coreboot.org/c/coreboot/+/72421/comment/ed2d6439_fbf29ceb
PS2, Line 286: acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP);
Can't we use `acpigen_write_not(LOCAL0_OP, LOCAL0_OP)` instead ?
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Martin L Roth has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72801 )
Change subject: util/testing: Allow scanbuild test to be skipped
......................................................................
util/testing: Allow scanbuild test to be skipped
This is currently killing the jenkins builds. This patch allows it to
be disabled until the reason is found.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I16dba80a88953aa95f7f647ba12b2ec3297ab81f
---
M util/testing/Makefile.inc
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/72801/2
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Change subject: util/testing: Allow scanbuild test to be skipped.
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169976):
https://review.coreboot.org/c/coreboot/+/72801/comment/e42921ec_521f6640
PS1, Line 6:
Subject line should not end with a period.
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Change subject: util/testing: Allow scanbuild test to be skipped.
......................................................................
util/testing: Allow scanbuild test to be skipped.
This is currently killing the jenkins builds. This patch allows it to
be disabled until the reason is found.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I16dba80a88953aa95f7f647ba12b2ec3297ab81f
---
M util/testing/Makefile.inc
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/72801/1
diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc
index 6f14c2d..ff55df0 100644
--- a/util/testing/Makefile.inc
+++ b/util/testing/Makefile.inc
@@ -115,7 +115,9 @@
util/lint/lint lint-extended $(JUNIT)
test-abuild:
+ifneq ($(JENKINS_SKIP_SCANBUILD_TEST),y)
NAME=scanbuild; SCANBUILD_ARGS='-k -plist-html -maxloop 10' util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -scan-build --target EMULATION_QEMU_X86_Q35 --exitcode --name $${NAME}
+endif
ifneq ($(JENKINS_SKIP_GCC_TESTS),y)
NAME=gcc-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -x --name $${NAME} --clean
NAME=gcc; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --name $${NAME} --clean-somewhat
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Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71925/comment/c1929832_8b6865a4
PS6, Line 17: osiris MLB: C1
Why not both ports? What is the criteria?
https://review.coreboot.org/c/coreboot/+/71925/comment/33b3cd1f_582503e7
PS6, Line 24: marasov
changes are missing for marasov.
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Change subject: [WIP] src/drivers/s3_save_restore: Initial support for SMM payload
......................................................................
Patch Set 8:
(2 comments)
File src/drivers/s3_save_restore/cbtable.c:
https://review.coreboot.org/c/coreboot/+/70378/comment/4dd1d691_e3a54abb
PS8, Line 52: void lb_save_restore(struct lb_header *header)
Everything in here is platform specific and could be
1) be part of Edk2Platforms and hardcode those values
2) be part of UefiPayloadPkg and detect those values by matching MCH/PCH IDs.
https://review.coreboot.org/c/coreboot/+/70378/comment/89c26e0a_c5663a47
PS8, Line 172: LB_TAG_PLD_NV_VARIABLE_INFO
there's no need for such table:
- The payload is coreboot aware
- The payload has a platform specific SPI driver
Thus the payload can find and parse the FMAP by itself.
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Change subject: soc/amd/phoenix/include/cpu: rename CPUID define to match CPU model
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Patch Set 1: Code-Review+1
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Change subject: mb/google/brya/var/kano: Update ELAN TS delay time to 150ms
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Please also update the datasheet in AVL and then mark this as resolved
Done
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