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Hello build bot (Jenkins), Subrata Banik, Jon Murphy, Nick Vaccaro, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: ec/google/chromeec: clang-format ec_commands.h
......................................................................
ec/google/chromeec: clang-format ec_commands.h
This is a format-only change: Reformat ec_commands.h using clang-format
according to the EC repo's current formatting style.
The comand is:
clang-format --style=file:$EC/.clang-format -i ec_commands.h
where $EC points to the chromeos EC repo.
The EC repo has recently adpoted the practice of formatting all files
through clang-format using its own style. So, run ec_commands.h through
the EC's clang-format so future updates don't get overwhelmed by
inconsequential style changes.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/ec/google/chromeec/ec_commands.h
1 file changed, 827 insertions(+), 838 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/72639/2
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Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72639 )
Change subject: ec/google/chromeec: clang-format ec_commands.h
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72639/comment/46a11bc7_445b3475
PS1, Line 14: future updates don't get overwhelmed
: by inconsequential style changes
> To solve the problem shouldn't we copy ec_commands. […]
either way, we need to run this file once through clang-format - either with
coreboot's config or the EC's config - so the next ec_commands.h refresh
patch isn't overwhelming.
if folks prefer this file to maintain the EC repo format, i'm fine with that.
Patchset:
PS1:
> Are you using this one https://review.coreboot. […]
no, i'm using the checked-in one.
File src/ec/google/chromeec/ec_commands.h:
https://review.coreboot.org/c/coreboot/+/72639/comment/789a5703_e6d01651
PS1, Line 96: #define EC_LPC_ADDR_HOST_PARAM
> consider moving the comment to a single line above this to prevent the weird wrapping: […]
since this patch is a strictly mechanical reformat,
we shouldn't apply this change here. we do get this
change for "free" with the ec_commands.h refresh
from the cros EC repo. that's the next patch.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72858 )
Change subject: cpu/intel/model_206ax: use CPUID_FROM_FMS macro instead of magic numbers
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
only added you to the last of the snb/ivb patches, but thought you might be interested in those. not planning to move the other intel socs over to the new functionality, but maybe you'll like the idea and port those over too. only planning to do that for the remaining amd socs, but the patch train already became a bit long
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Felix Held has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72854 )
Change subject: cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASK
......................................................................
cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASK
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry
per family & model combination and not one per stepping.
TEST=Thinkpad x230 with Ivy Bridge stepping 9 CPU still boots with this
patch applied.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I46020d5b1b1fba8449c3823fac1369e5670d91c0
---
M src/cpu/intel/model_206ax/model_206ax_init.c
1 file changed, 18 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/72854/2
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72784 )
Change subject: mb/google/brya/var/kano: Update ELAN TS delay time to 150ms
......................................................................
mb/google/brya/var/kano: Update ELAN TS delay time to 150ms
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the kano's delay time to follow
the requiremnet.
BUG=b:247944006
TEST=Manually checked touchscreen works after reboot and suspend.
Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paz Zcharya <pazz(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 23 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Eric Lai: Looks good to me, approved
Paz Zcharya: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index 2eca449..97682bd 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -400,7 +400,7 @@
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
- register "generic.reset_delay_ms" = "20"
+ register "generic.reset_delay_ms" = "150"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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Change subject: mb/google/brya/var/kano: Update ELAN TS delay time to 150ms
......................................................................
Patch Set 1: Code-Review+2
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72861 )
Change subject: soc/amd/phoenix/soc_util: add get_soc_type
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/amd/phoenix/soc_util: add get_soc_type
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/phoenix/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/72861/comment/8eef0218_06bb0288
PS1, Line 4: AMD_PHOENIX_SOC_UTIL_
> AMD_PHOENIX_SOC_UTIL_H
Done
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Hello Jason Glenesk, Matt DeVillier, Fred Reitberger,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/phoenix/soc_util: add get_soc_type
......................................................................
soc/amd/phoenix/soc_util: add get_soc_type
Implement a get_soc_type function to determine if the silicon the code
is running on is Phoenix or Phoenix 2. This will for example be needed
to provide the correct DXIO descriptor table for the SoC.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I5f2b668b83432426b04e7f1354b694ddd6c300d6
---
M src/soc/amd/phoenix/Makefile.inc
A src/soc/amd/phoenix/include/soc/soc_util.h
A src/soc/amd/phoenix/soc_util.c
3 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/72861/2
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Hello Jason Glenesk, Matt DeVillier, Fred Reitberger,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/picasso/soc_util: use cpuid_match
......................................................................
soc/amd/picasso/soc_util: use cpuid_match
Now that there is a cpuid_match function, we can use it instead of doing
basically the same thing manually.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62
---
M src/soc/amd/picasso/soc_util.c
1 file changed, 18 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/72860/2
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