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Change subject: sc7280: Update AOP firmware to version 454
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Patch Set 1: Verified+1
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Change subject: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
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Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
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Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/72441/comment/8ac8a8c6_47b0267c
PS5, Line 410: #if (CONFIG(SOC_INTEL_PCIE_64BIT_ALLOC))
> No need for the outer parens. Do this instead: […]
Done
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Change subject: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
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soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC.
In such case, is_pci64bit_alloc() return 1.
Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296
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---
M src/soc/intel/xeon_sp/chip_common.c
1 file changed, 22 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/72441/6
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Change subject: soc/intel/rtd3: Hook up supported states to Kconfig
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Patch Set 4: Code-Review+1
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Change subject: device/pnp,util/sconfig: introduce and use `REG8` resource type
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Patch Set 8:
(1 comment)
This change is ready for review.
File src/include/device/resource.h:
https://review.coreboot.org/c/coreboot/+/48925/comment/8aadfc1a_9cebc049
PS8, Line 18: #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
> oof, good catch!
Any idea if 0x00200000 would work? Were 0x00200000-0x00800000 left out on purpose?
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Change subject: mb/google/skyrim: Add support for and select USE_SELECTIVE_GOP_INIT
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Patch Set 9:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-170020):
https://review.coreboot.org/c/coreboot/+/70900/comment/969861c2_33b9f1b4
PS9, Line 9: Add a RW FMAP region to support caching GOP-driver-modified VBIOS tables.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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