coreboot-gerrit February 2023

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[M] Change in coreboot[master]: tree: Drop repeated words
by Elyes Haouas (Code Review) 07 Feb '23

07 Feb '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72795 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: tree: Drop repeated words ...................................................................... tree: Drop repeated words Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig M src/arch/arm/include/armv7/arch/cache.h M src/cpu/x86/Kconfig M src/include/device_tree.h M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/google/dedede/smihandler.c M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/prodrive/hermes/eeprom.c M src/soc/intel/common/block/cse/cse_lite.c M src/southbridge/amd/pi/hudson/lpc.c M src/vendorcode/eltan/security/mboot/mboot.c M tests/lib/rtc-test.c M util/sconfig/main.c 32 files changed, 72 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Frans Hendriks: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve Nicholas Chin: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 8246a17..16f7881 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -562,7 +562,7 @@ # Default value set at the end of the file help This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start + end of the ROM (passed through cbfstool -o) on x86 and at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index e332c31..f10b8a0 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -192,7 +192,7 @@ return val; } -/* read cache size ID register register (CCSIDR) */ +/* read cache size ID register (CCSIDR) */ static inline uint32_t read_ccsidr(void) { uint32_t val = 0; diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 7e58175..1a7d8c6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -179,7 +179,7 @@ bool default n help - This option limits the number of SIPI signals sent during during the + This option limits the number of SIPI signals sent during the common AP setup. Intel documentation specifies an INIT SIPI SIPI sequence, however this doesn't work on some AMD and Intel platforms. These newer AMD and Intel platforms don't need the 10ms wait between @@ -197,7 +197,7 @@ default n help This option allows a platform to reserve 2 MTRRs for the OS usage. - The Intel SDM documents that the the first 6 MTRRs are intended for + The Intel SDM documents that the first 6 MTRRs are intended for the system BIOS and the last 2 are to be reserved for OS usage. However, modern OSes use PAT to control cacheability instead of using MTRRs. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index ae30c59..02fcaa7 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -91,10 +91,10 @@ * which were consumed reading the requested value. */ -/* Read the property, if any, at offset offset. */ +/* Read the property at offset, if any exists. */ int fdt_next_property(const void *blob, uint32_t offset, struct fdt_property *prop); -/* Read the name of the node, if any, at offset offset. */ +/* Read the name of the node at offset, if any exists. */ int fdt_node_name(const void *blob, uint32_t offset, const char **name); void fdt_print_node(const void *blob, uint32_t offset); diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 4b1b9af..c408d5a 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -40,7 +40,7 @@ device ref ehci2 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c subsystemid 0x8086 0x7270 end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x8086 0x7270 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 163cdb3..b9f3f4d 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -57,7 +57,7 @@ device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x1849 0x8892 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 89ef419..cb30fc3 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,7 +5,7 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1b.0 on # High Definition Audio Audio controller + device pci 1b.0 on # High Definition Audio controller subsystemid 0x1043 0x8445 end device pci 1c.0 off end # PCIe Port #1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 98fcb62..bacdae8 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -11,7 +11,7 @@ { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 33c6b2e..7fc4c13 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -80,7 +80,7 @@ } /* - * Note that we are assuming that the Status Register protect bits are + * Note that we are assuming that the Status Register protect bits * are located at this index and that 1 means hardware protected. This * should be the case for these boards. */ diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 95d5368..74c601a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -168,7 +168,7 @@ register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 + # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. @@ -181,7 +181,7 @@ register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 + # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. @@ -207,7 +207,7 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. @@ -220,7 +220,7 @@ register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 + # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. @@ -233,7 +233,7 @@ register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 + # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 3ca1648..07ed7bc 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -10,7 +10,7 @@ register "PcieRpAdvancedErrorReporting[6]" = "1" # RP 7, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" - # RP 7 uses uses CLK SRC 4 + # RP 7 uses CLK SRC 4 register "PcieRpClkSrcNumber[6]" = "4" # Enable Root port 8(x1) for TPU0 @@ -23,7 +23,7 @@ register "PcieRpAdvancedErrorReporting[7]" = "1" # RP 8, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[7]" = "1" - # RP 8 uses uses CLK SRC 2 + # RP 8 uses CLK SRC 2 register "PcieRpClkSrcNumber[7]" = "2" # Enable Root port 9(x4) for i350 LAN @@ -34,7 +34,7 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # These are part of Root port 9(x4) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d963d9d..2e3953a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 25f75b8f..07363fd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -135,7 +135,7 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 66c07db..8be97c8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -133,7 +133,7 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7cc3eb3..a20c197 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -130,7 +130,7 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 13398d0..a18ec3c 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -30,7 +30,7 @@ device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 265b0ef..71b1865 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -34,7 +34,7 @@ device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index df35e8a..d512814 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -10,37 +10,37 @@ register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses uses CLK SRC 2 + # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses uses CLK SRC 3 + # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses uses CLK SRC 4 + # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses uses CLK SRC 5 + # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses uses CLK SRC 7 + # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" # USB related diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b1d2917..2c93a38 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -41,21 +41,21 @@ register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses uses CLK SRC 2 + # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses uses CLK SRC 3 + # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" # PCIE Port 7 Disabled @@ -64,14 +64,14 @@ register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses uses CLK SRC 5 + # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses uses CLK SRC 4 + # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" # USB 2.0 Enable all ports diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 5c5382f..23cbf96 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -101,15 +101,15 @@ register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkReqNumber[8]" = "1" - # RP 3 uses uses CLK SRC 5# + # RP 3 uses CLK SRC 5# register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses uses CLK SRC 2# + # RP 4 uses CLK SRC 2# register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses uses CLK SRC 3# + # RP 5 uses CLK SRC 3# register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses uses CLK SRC 4# + # RP 6 uses CLK SRC 4# register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses uses CLK SRC 1# + # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index fc00734..fb05027 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -41,7 +41,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio controller device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader device pci 1c.1 on # PCIe Port #2, WLAN smbios_slot_desc "0x14" "1" "M.2 2230" "8" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ca16094..a012741 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -41,7 +41,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 on end # PCIe Port #3 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f105424..eae9696 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -45,7 +45,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index bcffdaa..7e54383 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -43,7 +43,7 @@ device ref me_kt off end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 0acf98bb..beb2609 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 (WLAN card) device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index c90c69c..86e86f5 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -96,7 +96,7 @@ }" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" - # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) + # Enable CPU PCIE RP 1, 2, 3 using free running CLK (0x80) # Clock source is shared hence marked as free running. register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index c4a2695..c0e9cb6 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -16,7 +16,7 @@ /* * Check Signature in EEPROM (M24C32-FMN6TP) - * If signature is there we assume that that the content is valid + * If signature is there we assume that the content is valid */ int check_signature(const size_t offset, const uint64_t signature) { diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9866d55..4a624e6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1111,7 +1111,7 @@ /* * If system is in recovery mode, CSE Lite update has to be skipped but CSE - * sub-partitions like NPHY and IOM have to to be updated. If CSE sub-parition update + * sub-partitions like NPHY and IOM have to be updated. If CSE sub-parition update * fails during recovery, just continue to boot. */ if (CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE) && vboot_recovery_mode_enabled()) { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 7abb5bf..0a4e038 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -47,8 +47,8 @@ /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can + byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is running + on LPC, it holds PCI grant, so no LPC slave cycle can interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index d7817bd..e8a2f80 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -342,7 +342,7 @@ * * mb_measure_log_start * - * performs the measurements defined by the the board routines. + * performs the measurements defined by the board routines. * * The logging is defined by the mb_log_list structure * diff --git a/tests/lib/rtc-test.c b/tests/lib/rtc-test.c index c3c7403..a205692 100644 --- a/tests/lib/rtc-test.c +++ b/tests/lib/rtc-test.c @@ -109,7 +109,7 @@ tm.mon = 2; tm.mday = 29; assert_int_equal(1078062333, rtc_mktime(&tm)); - /* Ensure that February 29 and March 1 have different different and correct values + /* Ensure that February 29 and March 1 have different and correct values in leap year */ tm = (struct rtc_time){ .year = 2004, .mon = 3, .mday = 1, .hour = 7, .min = 7, .sec = 17, diff --git a/util/sconfig/main.c b/util/sconfig/main.c index a532dd4..6618a45 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -317,7 +317,7 @@ sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { /* root_complex gets away without a separate directory, but - * exists on on pretty much all AMD chipsets. + * exists on pretty much all AMD chipsets. */ if (!strstr(path, "/root_complex")) { fprintf(stderr, "ERROR: Chip component %s does not exist.\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/72795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Gerrit-Change-Number: 72795 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Ron Lee (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Nick Vaccaro. Ron Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71925/comment/8d2614bf_58055fa7 PS6, Line 17: osiris MLB: C1 > Why not both ports? What is the criteria? The LPM incapability so far is only for Type-C port with Parade PS8815 retimer, this port is usually located on DB. The list of impacted projects is provided by each project's TAM/HWE. https://review.coreboot.org/c/coreboot/+/71925/comment/92e36b0b_616d27b1 PS6, Line 24: marasov > changes are missing for marasov. Thanks for the reminder, add in patchset7 Patchset: PS6: > Why was this change not made for brya0? Confirmed with brya0 PM, brya0 has Type-C port with PS8815 retimer on DB, so add usb_lpm_incapable config as well. thx -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 7 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 03:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Ron Lee (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Ron Lee. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71925 to look at the new patch set (#7). Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. This patch add usb_lpm_incapable config for the following variants with PS8815 retimer: - kinox MLB: C0 - volmar DB: C1 - osiris MLB: C1 - mithrax DB: C1 - felwinter DB: C1 - taeko DB: C1 - gimble DB: C1 - gimble4es DB: C1 - taniks DB: C1 - marasov DB: C2 - gaelin MLB: C0/C1 - skolas DB: C1 - skolas4es DB: C1 - brya0 DB: C1 BUG=b:253402457 TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Signed-off-by: Ron Lee <ron.lee(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kinox/overridetree.cb M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/mithrax/overridetree.cb M src/mainboard/google/brya/variants/osiris/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb 14 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/71925/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 7 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: DEMO: Load MP2 fw by default
by Bao Zheng (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71920 ) Change subject: DEMO: Load MP2 fw by default ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Based on my test, it has to load the MP2 FW to boot on simulator. I don't quite know why. Is it need to merge? -- To view, visit https://review.coreboot.org/c/coreboot/+/71920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc779a7e0e12deb44b64b480ae9ca10d1ed0dbcb Gerrit-Change-Number: 71920 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 03:10:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/samsung: Enable VBOOT_VBNV_FLASH
by Yidi Lin (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Martin L Roth, Angel Pons, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70296 ) Change subject: mb/samsung: Enable VBOOT_VBNV_FLASH ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I833edd4f7a328b21e81c971ba8a9aec0aad7d3d3 Gerrit-Change-Number: 70296 Gerrit-PatchSet: 8 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 02:39:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: ec/google/chromeec: clang-format ec_commands.h
by Yu-Ping Wu (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Martin L Roth, Subrata Banik, Caveh Jalali, Nick Vaccaro, Elyes Haouas, Boris Mittelberg. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72639 ) Change subject: ec/google/chromeec: clang-format ec_commands.h ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72639/comment/63041173_a40c6b50 PS1, Line 14: future updates don't get overwhelmed : by inconsequential style changes > either way, we need to run this file once through clang-format - either with […] Thanks. Now I think this is better because CB:72640 becomes a pure sync from EC. -- To view, visit https://review.coreboot.org/c/coreboot/+/72639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06 Gerrit-Change-Number: 72639 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 02:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: ec/google/chromeec: Update ec_commands.h
by Yu-Ping Wu (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Subrata Banik, Caveh Jalali, Nick Vaccaro, Boris Mittelberg. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72640 ) Change subject: ec/google/chromeec: Update ec_commands.h ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60 Gerrit-Change-Number: 72640 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 02:36:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86/smbios: Modify smbios type 9 data bus width
by Shuming Chu (Shuming) (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Wilson Chou, Martin L Roth, Patrick Rudolph, Ryback Hung, Johnny Lin, Angel Pons, Arthur Heymans, Eric Lai. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71694 ) Change subject: arch/x86/smbios: Modify smbios type 9 data bus width ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c72c422e0fdc136f4ed42c5c6818423aabc2704 Gerrit-Change-Number: 71694 Gerrit-PatchSet: 4 Gerrit-Owner: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Wilson Chou <wilson.chou%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 02:02:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/soc_util: use cpuid_match
by Eric Lai (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72860 ) Change subject: soc/amd/picasso/soc_util: use cpuid_match ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/picasso/soc_util.c: https://review.coreboot.org/c/coreboot/+/72860/comment/dd6852fd_ffa60d4e PS4, Line 97: 0xffffff00 create another mask for this? -- To view, visit https://review.coreboot.org/c/coreboot/+/72860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62 Gerrit-Change-Number: 72860 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 01:59:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in qc_blobs[master]: sc7280: Update AOP firmware to version 454
by Shelley Chen (Code Review) 07 Feb '23

07 Feb '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/qc_blobs/+/72842 ) Change subject: sc7280: Update AOP firmware to version 454 ...................................................................... sc7280: Update AOP firmware to version 454 *L3C min voltage update to 1.8v Change-Id: I3748642f914e6e20a648b4fadc71cd87ffc80150 Signed-off-by: Sai Santhosh Vaginepalli <svaginep(a)hydcbspbld01.qualcomm.com> --- M sc7280/aop/AOP_AAAAANAAO.elf M sc7280/aop/AOP_AAAAANAZO.elf M sc7280/aop/Release_Notes.txt M sc7280/aop/aop.mbn 4 files changed, 34 insertions(+), 0 deletions(-) Approvals: Shelley Chen: Verified; Looks good to me, approved diff --git a/sc7280/aop/AOP_AAAAANAAO.elf b/sc7280/aop/AOP_AAAAANAAO.elf index 9f704c4..75086f4 100644 --- a/sc7280/aop/AOP_AAAAANAAO.elf +++ b/sc7280/aop/AOP_AAAAANAAO.elf Binary files differ diff --git a/sc7280/aop/AOP_AAAAANAZO.elf b/sc7280/aop/AOP_AAAAANAZO.elf index 28083e7..0f84c4b 100644 --- a/sc7280/aop/AOP_AAAAANAZO.elf +++ b/sc7280/aop/AOP_AAAAANAZO.elf Binary files differ diff --git a/sc7280/aop/Release_Notes.txt b/sc7280/aop/Release_Notes.txt index 94185ac..689a173 100644 --- a/sc7280/aop/Release_Notes.txt +++ b/sc7280/aop/Release_Notes.txt @@ -1,3 +1,25 @@ +================== Release 454 ================================ +This Release Notes file covers these blobs: + * aop.mbn + * AOP_AAAAANAZO.elf + +Version : 000454 + +Release Date : February, 2023 + +Supported Silicon : SC7280 + +Changes since last version: + *L3C min voltage update to 1.8V + +aop.mbn is used to generate coreboot image. +AOP_AAAAANAZO.elf is used for debugging purpose if needed. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report + ================== Release 410 ================================ This Release Notes file covers these blobs: * aop.mbn diff --git a/sc7280/aop/aop.mbn b/sc7280/aop/aop.mbn index dceb584..336f805 100644 --- a/sc7280/aop/aop.mbn +++ b/sc7280/aop/aop.mbn Binary files differ -- To view, visit https://review.coreboot.org/c/qc_blobs/+/72842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I3748642f914e6e20a648b4fadc71cd87ffc80150 Gerrit-Change-Number: 72842 Gerrit-PatchSet: 1 Gerrit-Owner: Santhosh Vaginepalli <svaginep(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Douglas Anderson <dianders(a)chromium.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2023