coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Add support to configure 6bit color depth
by Venkat Thogaru (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Shelley Chen. Hello Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72744 to look at the new patch set (#3). Change subject: soc/qualcomm/sc7280: Add support to configure 6bit color depth ...................................................................... soc/qualcomm/sc7280: Add support to configure 6bit color depth Some of the eDp panels use 6bit color depth as default. Set the default color depth configuration to 6 bit when there is no match with the supported color depths. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369 Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> --- M src/soc/qualcomm/sc7280/display/edp_ctrl.c 1 file changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/72744/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369 Gerrit-Change-Number: 72744 Gerrit-PatchSet: 3 Gerrit-Owner: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support
by Subrata Banik (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Marx Wang, Subrata Banik, Jamie Chen, Tarun Tuli, Ian Feng, Kyle Lin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72090 ) Change subject: mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Gerrit-Change-Number: 72090 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 06:08:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIe port 8 for WLAN
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72778 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/intel/mtlrvp: Enable PCIe port 8 for WLAN ...................................................................... mb/intel/mtlrvp: Enable PCIe port 8 for WLAN This patch enables PCIe port for WLAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets is enumerated as part of lspci in AP console. ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE Advanced Modem (rev 01) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 1573cdf..53464f9 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -87,6 +87,14 @@ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, }" end # WWAN + device ref pcie_rp8 on + # Enable PCH PCIE RP 8 using CLK 5 + register "pcie_rp[PCIE_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + end # WLAN device ref pcie_rp10 on # Enable SSD Gen4 PCIE 10 using CLK 8 register "pcie_rp[PCIE_RP(10)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/72778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74 Gerrit-Change-Number: 72778 Gerrit-PatchSet: 6 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72813 ) Change subject: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES ...................................................................... mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which helps in mode switch using dut-control power_state:rec. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode. Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Usha P: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 3468ac9..0d90a3b 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -90,6 +90,7 @@ config VBOOT select VBOOT_LID_SWITCH + select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/72813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Gerrit-Change-Number: 72813 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Harsha B R, Ravishankar Sarawadi, Felix Held. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72813 ) Change subject: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Gerrit-Change-Number: 72813 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 05:39:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72777 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/intel/mtlrvp: Enable PCIe port 7 for WWAN ...................................................................... mb/intel/mtlrvp: Enable PCIe port 7 for WWAN This patch enables PCIe port for WWAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module gets enumerated with cbmem -c. \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 628a8cb..1573cdf 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -79,6 +79,14 @@ device ref tcss_xhci on end device ref tcss_dma0 on end device ref tcss_dma1 on end + device ref pcie_rp7 on + # Enable PCH PCIE RP 7 using CLK 1 + register "pcie_rp[PCIE_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + end # WWAN device ref pcie_rp10 on # Enable SSD Gen4 PCIE 10 using CLK 8 register "pcie_rp[PCIE_RP(10)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/72777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Gerrit-Change-Number: 72777 Gerrit-PatchSet: 6 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI support for Type-C ports
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72789 ) Change subject: mb/intel/mtlrvp: Enable ACPI support for Type-C ports ...................................................................... mb/intel/mtlrvp: Enable ACPI support for Type-C ports This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/dsdt.asl M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 3 files changed, 59 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Usha P: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 945aa2e..3468ac9 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -13,6 +13,7 @@ config BOARD_INTEL_MTLRVP_P_EXT_EC select BOARD_INTEL_MTLRVP_COMMON + select DRIVERS_INTEL_PMC if BOARD_INTEL_MTLRVP_COMMON diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl index d253617..a367bbb 100644 --- a/src/mainboard/intel/mtlrvp/dsdt.asl +++ b/src/mainboard/intel/mtlrvp/dsdt.asl @@ -22,6 +22,7 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> } } diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb index b08d7ca..f51f18b 100644 --- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -3,8 +3,38 @@ device domain 0 on device ref soc_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] device pnp 0c09.0 on end end end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port4 as usb2_port + use tcss_usb3_port4 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Gerrit-Change-Number: 72789 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI support for Type-C ports
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Felix Held. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72789 ) Change subject: mb/intel/mtlrvp: Enable ACPI support for Type-C ports ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Gerrit-Change-Number: 72789 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Feb 2023 05:34:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0
by Rex-BC Chen (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72749 ) Change subject: mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0 ...................................................................... Patch Set 4: -Code-Review (1 comment) File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/72749/comment/c9459666_e043303c PS4, Line 60: ret = mipi_panel_reg_mask(MIPI_PANEL_I2C, MIPI_PANEL_SLAVE, 0x03, 0x30, 0xFF); we need to confirm this setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/72749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Gerrit-Change-Number: 72749 Gerrit-PatchSet: 4 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 05:28:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC
by Elyes Haouas (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, David Hendricks, Christian Walter, Arthur Heymans, Tim Chu. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72441 ) Change subject: soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOC ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: Maybe: static uint8_t is_pci64bit_alloc(void) { /* * For SPR-SP FSP which supports SOC_INTEL_PCIE_64BITS_ALLOC, * Pci64BitResourceAllocation field does not exist in IIO_UDS HOB. */ if CONFIG(SOC_INTEL_PCIE_64BIT_ALLOC) return 1; const IIO_UDS *hob = get_iio_uds(); return hob->PlatformData.Pci64BitResourceAllocation; } File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/72441/comment/de9f735f_be4fc805 PS6, Line 410: #if why "#if"? "else" is not needed after "return". -- To view, visit https://review.coreboot.org/c/coreboot/+/72441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Gerrit-Change-Number: 72441 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 05:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2023