coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable WWAN ACPI
by Krishna P Bhat D (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72779 ) Change subject: mb/intel/mtlrvp: Enable WWAN ACPI ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Gerrit-Change-Number: 72779 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:36:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: update PL1 minimum value
by AlanKY Lee (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik, Vinay Kumar, Jérémy Compostella, Sumeet R Pawnikar, Vidya Gopalakrishnan. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72727 ) Change subject: mb/google/brya/var/skolas: update PL1 minimum value ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Copied messages from https://partnerissuetracker.corp.google.com/issues/235311241#comment47. Hi Sumeet, We are fine with these changes as per comment#43. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/72727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da Gerrit-Change-Number: 72727 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:30:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/skolas: update dptf thermal settings
by AlanKY Lee (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Bora Guvendik, Subrata Banik, Jérémy Compostella, Sumeet R Pawnikar, Nick Vaccaro. AlanKY Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71692 ) Change subject: mb/google/brya/var/skolas: update dptf thermal settings ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Patchset: PS2: > Hi Alan, […] Copy messages form https://partnerissuetracker.corp.google.com/issues/235311241#comment47. Hi Sumeet, We are fine with these changes as per comment#43. Thank you. Patchset: PS5: Copied from https://partnerissuetracker.corp.google.com/issues/235311241#comment47. Hi Sumeet, We are fine with these changes as per comment#43. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/71692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c Gerrit-Change-Number: 71692 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0
by Yu-Ping Wu (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72749 ) Change subject: mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0 ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/72749/comment/d90b08f7_7c00416b PS4, Line 50: ret = mipi_panel_reg_mask(MIPI_PANEL_I2C, MIPI_PANEL_SLAVE, 0x00, 0x11, 0x1F); : if (ret < 0) : return; ``` if (mipi_panel_reg_mask(MIPI_PANEL_I2C, MIPI_PANEL_SLAVE, 0x00, 0x11, 0x1F) < 0) return; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/72749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Gerrit-Change-Number: 72749 Gerrit-PatchSet: 4 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
by Shuming Chu (Shuming) (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Subrata Banik, Simon Chou, TimLiu-SMCI, Jonathan Zhang, Johnny Lin, Paul Menzel, David Hendricks, Christian Walter, Angel Pons, Jian-Ming Wang, Arthur Heymans, Elyes Haouas. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71945 ) Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory ...................................................................... Patch Set 11: (18 comments) File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/71945/comment/10f88b53_bc1f57c8 PS8, Line 204: #define GPPC_H8 144 : #define GPPC_H9 145 : #define GPPC_H10 146 : #define GPPC_H11 147 : #define GPPC_H12 148 : #define GPPC_H13 149 : #define GPPC_H14 150 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/0acb1374_8b1b249b PS8, Line 227: #define GPP_J9 165 : #define GPP_J10 166 : #define GPP_J11 167 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/85692b3e_6147dd5d PS8, Line 234: #define GPP_J16 172 : #define GPP_J17 173 > GPP_J15 is the last pad configuration in EDS for GPIO community 4. […] Ack https://review.coreboot.org/c/coreboot/+/71945/comment/4088c547_b24f10eb PS8, Line 237: GPP_J17 > GPP_J15 Like GPP_E23, let's keep using GPP_J17 here due to it does exist. https://review.coreboot.org/c/coreboot/+/71945/comment/c2f3665d_377ec62e PS8, Line 241: #define GPP_I0 180 > Tim, could you check this? It can be found as unrouted GPIOs in #606161 Table 13-11. https://review.coreboot.org/c/coreboot/+/71945/comment/d77d9c7c_e9e05337 PS8, Line 244: define GPP_I3 183 : #define GPP_I4 184 : #define GPP_I5 185 : #define GPP_I6 186 : #define GPP_I7 187 : #define GPP_I8 188 : #define GPP_I9 189 : #define GPP_I10 190 : #define GPP_I11 191 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/0fb5abd3_b22352d8 PS8, Line 259: #define GPP_I18 198 : #define GPP_I19 199 : #define GPP_I20 200 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/ceb5a63a_361232e4 PS8, Line 276: #define GPP_L9 213 : #define GPP_L10 214 : #define GPP_L11 215 : #define GPP_L12 216 : #define GPP_L13 217 : #define GPP_L14 218 : #define GPP_L15 219 : #define GPP_L16 220 : #define GPP_L17 221 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/bc312e7a_46b00e96 PS8, Line 296: #define GPP_M9 231 : #define GPP_M10 232 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/43dc6d53_d048cac8 PS8, Line 300: #define GPP_M13 235 : #define GPP_M14 236 > They are not declared as unrouted GPIOs in EDS. […] I think they are unrouted GPIOs? Refer to #606161 Table 13-11. No matter what, it shall be fine to keep them. https://review.coreboot.org/c/coreboot/+/71945/comment/c81fc921_41d4ff0c PS8, Line 312: #define GPP_N5 245 : #define GPP_N6 246 : #define GPP_N7 247 : #define GPP_N8 248 : #define GPP_N9 249 : #define GPP_N10 250 : #define GPP_N11 251 : #define GPP_N12 252 : #define GPP_N13 253 : #define GPP_N14 254 : #define GPP_N15 255 : #define GPP_N16 256 : #define GPP_N17 257 > GPP_N4 is the last pad configuration in EDS for GPIO community 5. […] Ack https://review.coreboot.org/c/coreboot/+/71945/comment/d6d09328_d30de115 PS8, Line 326: GPP_N17 > GPP_N4 Like GPP_E23, let's keep using GPP_N17 here due to it does exist. File src/soc/intel/xeon_sp/ebg/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/71945/comment/f7735be9_1a055c94 PS6, Line 6: #define PID_CSME0 0x90 > Tim, could you check this? I suppose this is used by HECI? I check this definition comes from CB:61431 and it may build failed if we don't define this. File src/soc/intel/xeon_sp/ebg/soc_gpio.c: https://review.coreboot.org/c/coreboot/+/71945/comment/ef0b3705_cef51706 PS8, Line 24: SPI0_IO_2 > GPPC_S0? See comments in gpio_soc_defs.h. Done https://review.coreboot.org/c/coreboot/+/71945/comment/429b9654_fb3f9bd6 PS8, Line 38: GPP_J17 > GPPC_J15? See comments in gpio_soc_defs.h. As comments in gpio_soc_defs.h, let's keep GPP_J17 here. https://review.coreboot.org/c/coreboot/+/71945/comment/22e925d9_c648eb41 PS8, Line 45: GPP_N17 > GPPC_N4? See comments in gpio_soc_defs.h. As comments in gpio_soc_defs.h, let's keep GPP_N17 here. https://review.coreboot.org/c/coreboot/+/71945/comment/dc672d68_88512d12 PS8, Line 113: GPP_J17 > GPP_J15? See comments in gpio_soc_defs.h. As comments in gpio_soc_defs.h, let's keep GPP_J17 here. https://review.coreboot.org/c/coreboot/+/71945/comment/10cae6f7_44a90b50 PS8, Line 131: .first_pad = GPP_I0, : .last_pad = GPP_N17, > GPP_I1 to GPP_N4? See comments in gpio_soc_defs.h. As comments in gpio_soc_defs.h, let's keep GPP_I0/GPP_N17 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/71945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Gerrit-Change-Number: 71945 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:20:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface
by Sridhar Siricilla (Code Review) 07 Feb '23

07 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72706 ) Change subject: mb/intel/mtlrvp: Enable GSPI interface ...................................................................... mb/intel/mtlrvp: Enable GSPI interface This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223) SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 53464f9..ddb80026 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -69,6 +69,21 @@ }, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -129,6 +144,7 @@ device ref i2c5 on end device ref shared_sram on end device ref uart0 on end + device ref gspi1 on end device ref smbus on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Gerrit-Change-Number: 72706 Gerrit-PatchSet: 6 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update gpio table
by Amanda Hwang (Code Review) 07 Feb '23

07 Feb '23

Amanda Hwang has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72865 ) Change subject: mb/google/dedede/var/dibbi: Update gpio table ...................................................................... mb/google/dedede/var/dibbi: Update gpio table Config GPP_B9 as LAN_CLKREQ_ODL based on latest schematic BUG=265021899 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/dibbi/gpio.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/72865/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Gerrit-Change-Number: 72865 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Kapil Porwal (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Ron Lee, Nick Vaccaro. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 7 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 07:04:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update gpio table
by Amanda Hwang (Code Review) 07 Feb '23

07 Feb '23

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72865 ) Change subject: mb/google/dedede/var/dibbi: Update gpio table ...................................................................... mb/google/dedede/var/dibbi: Update gpio table Update gpio config based on latest schematic 1. Config GPP_B9 as LAN_CLKREQ_ODL 2. Config GPP_H12 as CNF_RF_RESET_N BUG=265021899 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/dibbi/gpio.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/72865/1 diff --git a/src/mainboard/google/dedede/variants/dibbi/gpio.c b/src/mainboard/google/dedede/variants/dibbi/gpio.c index f1a6516..722e659 100644 --- a/src/mainboard/google/dedede/variants/dibbi/gpio.c +++ b/src/mainboard/google/dedede/variants/dibbi/gpio.c @@ -16,6 +16,9 @@ /* A18 : USB_OC0_N */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* B9 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* D2 : PWM_PP3300_BUZZER */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D4 : LAN_PE_ISOLATE_ODL_R */ @@ -65,6 +68,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ PAD_NC(GPP_H7, NONE), + /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2), /* H15 : I2S_SPK_BCLK */ PAD_NC(GPP_H15, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/72865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Gerrit-Change-Number: 72865 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815
by Kapil Porwal (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Tarun Tuli, Ron Lee, Nick Vaccaro. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71925 ) Change subject: mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815 ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71925/comment/e4b6b96e_4d12cb52 PS6, Line 17: osiris MLB: C1 > The LPM incapability so far is only for Type-C port with Parade PS8815 retimer, this port is usually […] After looking at "experiment spreadsheet", it seems like the port C0 is not impacted even though it has the PS8815 retimer. -- To view, visit https://review.coreboot.org/c/coreboot/+/71925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Gerrit-Change-Number: 71925 Gerrit-PatchSet: 7 Gerrit-Owner: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ron Lee <ron.lee(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 07 Feb 2023 06:36:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Ron Lee <ron.lee(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023