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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: mb/google/rex: add support for UWB
......................................................................
mb/google/rex: add support for UWB
UWB on Rex will have 2 options to connect to the SoC.
1. Through gspi1 (muxed with FP)
2. bit-bang over GPP
This CL adds both options.
BUG=b/263413448
TEST=Waiting for HW to be available
Change-Id: I5d04007c11e7a2715cc897232896f40d77e1d725
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/rex0/Makefile.inc
A src/mainboard/google/rex/variants/rex0/fw_config.c
M src/mainboard/google/rex/variants/rex0/gpio.c
M src/mainboard/google/rex/variants/rex0/overridetree.cb
5 files changed, 102 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/72420/10
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Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik, Kapil Porwal.
Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72420
to look at the new patch set (#9).
Change subject: mb/google/rex: add support for UWB
......................................................................
mb/google/rex: add support for UWB
UWB on Rex will have 2 options to connect to the SoC.
1. Through gspi1 (muxed with FP)
2. bit-bang over GPP
This CL adds both options.
BUG=b/263413448
TEST=Waiting for HW to be available
Change-Id: I5d04007c11e7a2715cc897232896f40d77e1d725
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/rex0/Makefile.inc
A src/mainboard/google/rex/variants/rex0/fw_config.c
M src/mainboard/google/rex/variants/rex0/gpio.c
M src/mainboard/google/rex/variants/rex0/overridetree.cb
5 files changed, 103 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/72420/9
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72722 )
Change subject: soc/intel/common: Add Intel Trace Hub driver
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
IIRC, TH has been part of the memory map for a long time. Isn't this
conflicting with the cbmem_top()..TOLUD range in systemagent/?
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Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Anil Kumar K, Jérémy Compostella, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72826
to look at the new patch set (#7).
Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
......................................................................
src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
_ON() calls _STA() at the beginning. If _STA() indicates the device is
ON, it exits immediately. Before exiting, it needs to check if it was
scheduled to be skipped first.
NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following
by a device reset such as WWAN device. When such device calls its
_RST(), it increments OFSK. When the following _OFF() is called, it
was scheduled to skip, it will also increments ONSK. Similarly, when
the following _ON() is called, it checks if the previous _OFF was
skipped or not. If skipped, it needs to do the same. In normal
suspend/resume cases, these two variables remains '0'. No _OFF() and
_ON() calls are skipped.
entire generated code:
Method (_ON, 0, Serialized) // _ON_: Power On
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
If ((ONSK > Zero))
{
ONSK--
}
Return (One)
}
If ((ONSK == Zero))
{
Acquire (\_SB.PCI0.R3MX, 0xFFFF)
EMPG = Zero
Local7 = 0x06
While ((Local7 > Zero))
{
If ((AMPG == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
Release (\_SB.PCI0.R3MX)
\_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020,
0x00000020, 0x00000020)
\_SB.PCI0.STXS (0x015E)
If ((NCB7 == One))
{
L23R = One
Local7 = 0x14
While ((Local7 > Zero))
{
If ((L23R == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
NCB7 = Zero
Local7 = 0x08
While ((Local7 > Zero))
{
If ((LASX == One))
{
Break
}
Sleep (0x10)
Local7--
}
}
}
Else
{
ONSK--
}
}
BUG=b:241850118
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72826/7
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I'd like you to reexamine a change. Please visit
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Change subject: src/acpi: add function gen: if_lgreater_ and namestr assignment
......................................................................
src/acpi: add function gen: if_lgreater_ and namestr assignment
1. add functions to generate if greater than conditions:
acpigen_write_if_lgreater_op_op:
if (op1 > op2)
acpigen_write_if_lgreater_op_int:
if (op > val)
acpigen_write_if_lgreater_namestr_int:
if (namestr > val)
2. add function to assignal value to a namestr
acpigen_write_store_namestr_to_op:
namestr = val
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818
---
M src/acpi/acpigen.c
M src/include/acpi/acpigen.h
2 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/72825/5
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Hello Bora Guvendik, Lance Zhao, build bot (Jenkins), Hannah Williams, Anil Kumar K, Jérémy Compostella, Tim Wawrzynczak, Anil Kumar K, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72825
to look at the new patch set (#3).
Change subject: src/acpi: add function gen: if_lgreater_ and namestr assignment
......................................................................
src/acpi: add function gen: if_lgreater_ and namestr assignment
1. add functions to generate if greater than conditions:
acpigen_write_if_lgreater_op_op:
if (op1 > op2)
acpigen_write_if_lgreater_op_int:
if (op > val)
acpigen_write_if_lgreater_namestr_int:
if (namestr > val)
2. add function to assignal value to a namestr
acpigen_write_store_namestr_to_op:
namestr = val
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818
---
M src/acpi/acpigen.c
M src/include/acpi/acpigen.h
2 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/72825/3
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72757 )
Change subject: acpi/acpigen.h: Drop deprecated ACPI OP codes
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-170111):
https://review.coreboot.org/c/coreboot/+/72757/comment/6d3aaf0b_ce2ac953
PS6, Line 9: Clean up OP codes according to ACPI specs:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72757 )
Change subject: acpi/acpigen.h: Drop deprecated ACPI OP codes
......................................................................
Patch Set 5:
(1 comment)
File src/include/acpi/acpigen.h:
https://review.coreboot.org/c/coreboot/+/72757/comment/88232c54_98874ca0
PS4, Line 49: EVENT_OP = 0x02,
> Thx […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72757
to look at the new patch set (#6).
Change subject: acpi/acpigen.h: Drop deprecated ACPI OP codes
......................................................................
acpi/acpigen.h: Drop deprecated ACPI OP codes
Clean up OP codes according to ACPI specs:
https://uefi.org/specs/ACPI/6.5/20_AML_Specification.html?highlight=aml%20b…
Change-Id: I51e7f8dc6c0bfef0816ab4da6d96cb0fac873ee8
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/include/acpi/acpigen.h
1 file changed, 13 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/72757/6
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