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[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 24 Dec '23

24 Dec '23

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/dell/e7240.md M Documentation/mainboard/index.md A src/mainboard/dell/e7240/Kconfig A src/mainboard/dell/e7240/Kconfig.name A src/mainboard/dell/e7240/Makefile.inc A src/mainboard/dell/e7240/acpi/ec.asl A src/mainboard/dell/e7240/acpi/platform.asl A src/mainboard/dell/e7240/acpi/superio.asl A src/mainboard/dell/e7240/board_info.txt A src/mainboard/dell/e7240/bootblock.c A src/mainboard/dell/e7240/devicetree.cb A src/mainboard/dell/e7240/dsdt.asl A src/mainboard/dell/e7240/gma-mainboard.ads A src/mainboard/dell/e7240/gpio.c A src/mainboard/dell/e7240/hda_verb.c A src/mainboard/dell/e7240/romstage.c 16 files changed, 468 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79746/1 diff --git a/Documentation/mainboard/dell/e7240.md b/Documentation/mainboard/dell/e7240.md new file mode 100644 index 0000000..0fbbc76 --- /dev/null +++ b/Documentation/mainboard/dell/e7240.md @@ -0,0 +1,82 @@ +# Dell Latitude E7240 + +This page is about the notebook [Dell Latitude E7240]. + +## Release status + +Dell Latitude E7240 was released in 2013 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: +1. mrc.bin +2. Intel ME firmware + +Memory reference code in mrc.bin is used to initialize the Haswell platform. +You need this blob to build a working coreboot image. Please read +[mrc.bin](../../northbridge/intel/haswell/mrc.bin) for instructions on +retrieving and using it. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. +It can be extracted from the OEM firmware. You can also flash only the BIOS +region to leave Intel ME firmware untouched. + +## Programming + +The laptop can be flashed internally under OEM firmware using [dell-flash-unlock]. + +To flash with a programmer, you need to remove the battery and the base cover. + +For more details have a look at the general [flashing tutorial]. + +It is also possible to flash internally under coreboot. + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is next to the miniDP port. + +There's a serial port on dock, but it's not supported yet in coreboot. + +Schematic of this laptop can be found on [Lab One]. The board name is Compal LA-9431P. + +## Test status + +### Not working + +- EC ACPI +- Touchpad and the buttons on it +- SD/MMC card reader (kernel reports "Timeout waiting for hardware cmd interrupt.") +- No internal display before booting to OS when connected with a dock + +### Working + +- Integrated graphics init with libgfxinit +- mSATA +- WLAN +- USB +- Keyboard +- Dock: all USB ports, DisplayPort, eSATA +- Internal flashing when IFD is unlocked + + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC5075 | ++------------------+-----------------------------+ +| Super I/O | SMSC ECE5048 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[Dell Latitude E7240]: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… +[dell-flash-unlock]: https://github.com/nic3-14159/dell-flash-unlock +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Lab One]: https://www.laboneinside.com/dell-latitude-e7240-schematic-diagram/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 519d888..e523a43 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -45,6 +45,7 @@ ## Dell +- [Latitude E7240](dell/e7240.md) - [OptiPlex 9010 SFF](dell/optiplex_9010.md) ## Emulation diff --git a/src/mainboard/dell/e7240/Kconfig b/src/mainboard/dell/e7240/Kconfig new file mode 100644 index 0000000..23e4f41 --- /dev/null +++ b/src/mainboard/dell/e7240/Kconfig @@ -0,0 +1,36 @@ +if BOARD_DELL_LATITUDE_E7240 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_DELL_MEC5035 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "dell/e7240" + +config MAINBOARD_PART_NUMBER + string + default "Latitude E7240" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +endif diff --git a/src/mainboard/dell/e7240/Kconfig.name b/src/mainboard/dell/e7240/Kconfig.name new file mode 100644 index 0000000..83ab935 --- /dev/null +++ b/src/mainboard/dell/e7240/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_LATITUDE_E7240 + bool "Latitude E7240" diff --git a/src/mainboard/dell/e7240/Makefile.inc b/src/mainboard/dell/e7240/Makefile.inc new file mode 100644 index 0000000..ec8ca22 --- /dev/null +++ b/src/mainboard/dell/e7240/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/e7240/acpi/ec.asl b/src/mainboard/dell/e7240/acpi/ec.asl new file mode 100644 index 0000000..24915c2 --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/ec.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* FIXME: not working yet */ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 39) + + Method (_Q66, 0, NotSerialized) + { + Store ("EC: _Q66", Debug) + } +} diff --git a/src/mainboard/dell/e7240/acpi/platform.asl b/src/mainboard/dell/e7240/acpi/platform.asl new file mode 100644 index 0000000..2d24bbd --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/e7240/acpi/superio.asl b/src/mainboard/dell/e7240/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/e7240/board_info.txt b/src/mainboard/dell/e7240/board_info.txt new file mode 100644 index 0000000..46e950a --- /dev/null +++ b/src/mainboard/dell/e7240/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/dell/e7240/bootblock.c b/src/mainboard/dell/e7240/bootblock.c new file mode 100644 index 0000000..9c81c7f --- /dev/null +++ b/src/mainboard/dell/e7240/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + /* port 0x910 and 0x911 is needed to initialize the EC */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901); + mec5035_early_init(); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x005c0921); +} diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb new file mode 100644 index 0000000..6b0c5dd --- /dev/null +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -0,0 +1,71 @@ +chip northbridge/intel/haswell + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + device domain 0x0 on + ops haswell_pci_domain_ops + subsystemid 0x1028 0x05ca inherit + + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" + + register "alt_gp_smi_en" = "0x00002000" + register "gpe0_en_1" = "0x00000100" + register "gpe0_en_2" = "0x00000080" + register "gpe0_en_4" = "0x00000042" + + # 0(eSATA on dock), 1(mSATA near the fan), 3(mSATA near WLAN) + register "sata_port_map" = "0x0b" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 on end # PCIe Port #5, SD/MMC Card Reader + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/e7240/dsdt.asl b/src/mainboard/dell/e7240/dsdt.asl new file mode 100644 index 0000000..ef41b37 --- /dev/null +++ b/src/mainboard/dell/e7240/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/e7240/gma-mainboard.ads b/src/mainboard/dell/e7240/gma-mainboard.ads new file mode 100644 index 0000000..cdc7f18 --- /dev/null +++ b/src/mainboard/dell/e7240/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI1, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/e7240/gpio.c b/src/mainboard/dell/e7240/gpio.c new file mode 100644 index 0000000..1665025 --- /dev/null +++ b/src/mainboard/dell/e7240/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = LP_GPIO_OUT_LOW, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/e7240/hda_verb.c b/src/mainboard/dell/e7240/hda_verb.c new file mode 100644 index 0000000..7fd135a --- /dev/null +++ b/src/mainboard/dell/e7240/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805ca, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805ca), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/e7240/romstage.c new file mode 100644 index 0000000..da350a0 --- /dev/null +++ b/src/mainboard/dell/e7240/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, /* right, EHCI debug */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, /* back right, dock back */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, /* right */ + { 1, 0 }, /* back left */ + { 1, 2 }, /* back right, dock back */ + { 1, USB_OC_PIN_SKIP } +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: sb/intel/bd82x6x: Add defines for PCI IDs
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79546?usp=email ) Change subject: sb/intel/bd82x6x: Add defines for PCI IDs ...................................................................... sb/intel/bd82x6x: Add defines for PCI IDs Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/southbridge/intel/bd82x6x/lpc.c 2 files changed, 82 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e2836c8..ae74901 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2816,6 +2816,50 @@ #define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 #define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 +/* Intel Mobile 6 Series Chipset and 7 Series Chipset */ +#define PCI_DID_INTEL_6_SERIES_MOBILE_SFF 0x1c41 +#define PCI_DID_INTEL_6_SERIES_MOBILE 0x1c43 +#define PCI_DID_INTEL_6_SERIES_UM67 0x1c47 +#define PCI_DID_INTEL_6_SERIES_HM65 0x1c49 +#define PCI_DID_INTEL_6_SERIES_HM67 0x1c4b +#define PCI_DID_INTEL_6_SERIES_QS67 0x1c4d +#define PCI_DID_INTEL_6_SERIES_QM67 0x1c4f + +#define PCI_DID_INTEL_7_SERIES_MOBILE 0x1e42 +#define PCI_DID_INTEL_7_SERIES_MOBILE_SFF 0x1e43 +#define PCI_DID_INTEL_7_SERIES_QM77 0x1e55 +#define PCI_DID_INTEL_7_SERIES_QS77 0x1e56 +#define PCI_DID_INTEL_7_SERIES_HM77 0x1e57 +#define PCI_DID_INTEL_7_SERIES_UM77 0x1e58 +#define PCI_DID_INTEL_7_SERIES_HM76 0x1e59 +#define PCI_DID_INTEL_7_SERIES_HM75 0x1e5d +#define PCI_DID_INTEL_7_SERIES_HM70 0x1e5e +#define PCI_DID_INTEL_7_SERIES_NM70 0x1e5f + +/* Intel Desktop/Server 6 Series Chipset and 7 Series Chipset */ + +#define PCI_DID_INTEL_6_DESKTOP_SAMPLE 0x1c42 +#define PCI_DID_INTEL_6_SERIES_Z68 0x1c44 +#define PCI_DID_INTEL_6_SERIES_P67 0x1c46 +#define PCI_DID_INTEL_6_SERIES_H67 0x1c4a +#define PCI_DID_INTEL_6_SERIES_Q65 0x1c4c +#define PCI_DID_INTEL_6_SERIES_Q67 0x1c4e +#define PCI_DID_INTEL_6_SERIES_B65 0x1c50 +#define PCI_DID_INTEL_6_SERIES_C202 0x1c52 +#define PCI_DID_INTEL_6_SERIES_C204 0x1c54 +#define PCI_DID_INTEL_6_SERIES_C206 0x1c56 +#define PCI_DID_INTEL_6_SERIES_H61 0x1c5c + +#define PCI_DID_INTEL_7_SERIES_DESKTOP_SAMPLE 0x1e41 +#define PCI_DID_INTEL_7_SERIES_Z77 0x1e44 +#define PCI_DID_INTEL_7_SERIES_H71 0x1e45 +#define PCI_DID_INTEL_7_SERIES_Z75 0x1e46 +#define PCI_DID_INTEL_7_SERIES_Q77 0x1e47 +#define PCI_DID_INTEL_7_SERIES_Q75 0x1e48 +#define PCI_DID_INTEL_7_SERIES_B75 0x1e49 +#define PCI_DID_INTEL_7_SERIES_H77 0x1e4a +#define PCI_DID_INTEL_7_SERIES_C216 0x1e53 + /* Intel SDMA device Ids */ #define PCI_DID_INTEL_LPT_LP_SDMA 0x9c60 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5d1a7bf..69c9d44 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -432,44 +432,45 @@ * October 2013 * CDI / IBP#: 440377 */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, + {PCI_DID_INTEL_6_SERIES_MOBILE_SFF, "SFF Sample"}, + {PCI_DID_INTEL_6_DESKTOP_SAMPLE, "Desktop Sample"}, + {PCI_DID_INTEL_6_SERIES_MOBILE, "Mobile Sample"}, + {PCI_DID_INTEL_6_SERIES_Z68, "Z68"}, + {PCI_DID_INTEL_6_SERIES_P67, "P67"}, + {PCI_DID_INTEL_6_SERIES_UM67, "UM67"}, + {PCI_DID_INTEL_6_SERIES_HM65, "HM65"}, + {PCI_DID_INTEL_6_SERIES_H67, "H67"}, + {PCI_DID_INTEL_6_SERIES_HM67, "HM67"}, + {PCI_DID_INTEL_6_SERIES_Q65, "Q65"}, + {PCI_DID_INTEL_6_SERIES_QS67, "QS67"}, + {PCI_DID_INTEL_6_SERIES_Q67, "Q67"}, + {PCI_DID_INTEL_6_SERIES_QM67, "QM67"}, + {PCI_DID_INTEL_6_SERIES_B65, "B65"}, + {PCI_DID_INTEL_6_SERIES_C202, "C202"}, + {PCI_DID_INTEL_6_SERIES_C204, "C204"}, + {PCI_DID_INTEL_6_SERIES_C206, "C206"}, + {PCI_DID_INTEL_6_SERIES_H61, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, + {PCI_DID_INTEL_7_SERIES_DESKTOP_SAMPLE, "Desktop Sample"}, + {PCI_DID_INTEL_7_SERIES_MOBILE, "Mobile Sample"}, + {PCI_DID_INTEL_7_SERIES_MOBILE_SFF, "SFF Sample"}, + {PCI_DID_INTEL_7_SERIES_Z77, "Z77"}, + {PCI_DID_INTEL_7_SERIES_H71, "H71"}, + {PCI_DID_INTEL_7_SERIES_Z75, "Z75"}, + {PCI_DID_INTEL_7_SERIES_Q77, "Q77"}, + {PCI_DID_INTEL_7_SERIES_Q75, "Q75"}, + {PCI_DID_INTEL_7_SERIES_B75, "B75"}, + {PCI_DID_INTEL_7_SERIES_H77, "H77"}, + {PCI_DID_INTEL_7_SERIES_C216, "C216"}, + {PCI_DID_INTEL_7_SERIES_QM77, "QM77"}, + {PCI_DID_INTEL_7_SERIES_QS77, "QS77"}, + {PCI_DID_INTEL_7_SERIES_UM77, "UM77"}, + {PCI_DID_INTEL_7_SERIES_HM77, "HM77"}, + {PCI_DID_INTEL_7_SERIES_HM76, "HM76"}, + {PCI_DID_INTEL_7_SERIES_HM75, "HM75"}, + {PCI_DID_INTEL_7_SERIES_HM70, "HM70"}, + {PCI_DID_INTEL_7_SERIES_NM70, "NM70"}, }; static void report_pch_info(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/79546?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Gerrit-Change-Number: 79546 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: nb/intel/{gm45,sandybridge}: Use same indent levels for switch/case
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79444?usp=email ) Change subject: nb/intel/{gm45,sandybridge}: Use same indent levels for switch/case ...................................................................... nb/intel/{gm45,sandybridge}: Use same indent levels for switch/case Use same indent levels for switch/case in order to comply with the linter. Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/sandybridge/bootblock.c 4 files changed, 138 insertions(+), 138 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index eb1aa0a..69c817f 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -10,10 +10,10 @@ static uint32_t encode_pciexbar_length(void) { switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { - case 256: return 0 << 1; - case 128: return 1 << 1; - case 64: return 2 << 1; - default: return dead_code_t(uint32_t); + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); } } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7688d43..a998d77 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -71,37 +71,37 @@ else sysinfo->gfx_type = GMCH_UNKNOWN; switch (sysinfo->gfx_type) { - case GMCH_GM45: - printk(BIOS_SPEW, "GMCH: GM45\n"); - break; - case GMCH_GM47: - printk(BIOS_SPEW, "GMCH: GM47\n"); - break; - case GMCH_GM49: - printk(BIOS_SPEW, "GMCH: GM49\n"); - break; - case GMCH_GE45: - printk(BIOS_SPEW, "GMCH: GE45\n"); - break; - case GMCH_GL40: - printk(BIOS_SPEW, "GMCH: GL40\n"); - break; - case GMCH_GL43: - printk(BIOS_SPEW, "GMCH: GL43\n"); - break; - case GMCH_GS40: - printk(BIOS_SPEW, "GMCH: GS40\n"); - break; - case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", - sysinfo->gs45_low_power_mode ? "low" : "high"); - break; - case GMCH_PM45: - printk(BIOS_SPEW, "GMCH: PM45\n"); - break; - case GMCH_UNKNOWN: - printk(BIOS_SPEW, "unknown GMCH\n"); - break; + case GMCH_GM45: + printk(BIOS_SPEW, "GMCH: GM45\n"); + break; + case GMCH_GM47: + printk(BIOS_SPEW, "GMCH: GM47\n"); + break; + case GMCH_GM49: + printk(BIOS_SPEW, "GMCH: GM49\n"); + break; + case GMCH_GE45: + printk(BIOS_SPEW, "GMCH: GE45\n"); + break; + case GMCH_GL40: + printk(BIOS_SPEW, "GMCH: GL40\n"); + break; + case GMCH_GL43: + printk(BIOS_SPEW, "GMCH: GL43\n"); + break; + case GMCH_GS40: + printk(BIOS_SPEW, "GMCH: GS40\n"); + break; + case GMCH_GS45: + printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", + sysinfo->gs45_low_power_mode ? "low" : "high"); + break; + case GMCH_PM45: + printk(BIOS_SPEW, "GMCH: PM45\n"); + break; + case GMCH_UNKNOWN: + printk(BIOS_SPEW, "unknown GMCH\n"); + break; } sysinfo->txt_enabled = !(capid & (1 << (37-32))); @@ -110,25 +110,25 @@ } switch (render_freq) { - case 4: - sysinfo->max_render_mhz = 800; - break; - case 0: - sysinfo->max_render_mhz = 667; - break; - case 1: - sysinfo->max_render_mhz = 533; - break; - case 2: - sysinfo->max_render_mhz = 400; - break; - case 3: - sysinfo->max_render_mhz = 333; - break; - default: - printk(BIOS_SPEW, "Unknown render frequency\n"); - sysinfo->max_render_mhz = 0; - break; + case 4: + sysinfo->max_render_mhz = 800; + break; + case 0: + sysinfo->max_render_mhz = 667; + break; + case 1: + sysinfo->max_render_mhz = 533; + break; + case 2: + sysinfo->max_render_mhz = 400; + break; + case 3: + sysinfo->max_render_mhz = 333; + break; + default: + printk(BIOS_SPEW, "Unknown render frequency\n"); + sysinfo->max_render_mhz = 0; + break; } if (sysinfo->max_render_mhz != 0) { printk(BIOS_SPEW, "Render frequency: %d MHz\n", sysinfo->max_render_mhz); @@ -146,17 +146,17 @@ u32 ddr_cap = capid>>30 & 0x3; switch (ddr_cap) { - case 0: - sysinfo->max_ddr3_mt = 1067; - break; - case 1: - sysinfo->max_ddr3_mt = 800; - break; - case 2: - case 3: - printk(BIOS_SPEW, "GMCH not DDR3 capable\n"); - sysinfo->max_ddr3_mt = 0; - break; + case 0: + sysinfo->max_ddr3_mt = 1067; + break; + case 1: + sysinfo->max_ddr3_mt = 800; + break; + case 2: + case 3: + printk(BIOS_SPEW, "GMCH not DDR3 capable\n"); + sysinfo->max_ddr3_mt = 0; + break; } if (sysinfo->max_ddr3_mt != 0) { printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); @@ -164,18 +164,18 @@ const unsigned int max_fsb = (capid >> 28) & 0x3; switch (max_fsb) { - case 1: - sysinfo->max_fsb_mhz = 1067; - break; - case 2: - sysinfo->max_fsb_mhz = 800; - break; - case 3: - sysinfo->max_fsb_mhz = 667; - break; - default: - die("unknown FSB capability\n"); - break; + case 1: + sysinfo->max_fsb_mhz = 1067; + break; + case 2: + sysinfo->max_fsb_mhz = 800; + break; + case 3: + sysinfo->max_fsb_mhz = 667; + break; + default: + die("unknown FSB capability\n"); + break; } if (sysinfo->max_fsb_mhz != 0) { printk(BIOS_SPEW, "GMCH supports FSB with up to %d MHz\n", sysinfo->max_fsb_mhz); @@ -515,10 +515,10 @@ static mem_clock_t clock_index(const unsigned int clock) { switch (clock) { - case 533: return MEM_CLOCK_533MHz; - case 400: return MEM_CLOCK_400MHz; - case 333: return MEM_CLOCK_333MHz; - default: die("Unknown clock value.\n"); + case 533: return MEM_CLOCK_533MHz; + case 400: return MEM_CLOCK_400MHz; + case 333: return MEM_CLOCK_333MHz; + default: die("Unknown clock value.\n"); } return -1; /* Won't be reached. */ } @@ -567,9 +567,9 @@ sysinfo->selected_timings.fsb_clock = read_fsb_clock(); unsigned int fsb_mhz = 0; switch (sysinfo->selected_timings.fsb_clock) { - case FSB_CLOCK_1067MHz: fsb_mhz = 1067; break; - case FSB_CLOCK_800MHz: fsb_mhz = 800; break; - case FSB_CLOCK_667MHz: fsb_mhz = 667; break; + case FSB_CLOCK_1067MHz: fsb_mhz = 1067; break; + case FSB_CLOCK_800MHz: fsb_mhz = 800; break; + case FSB_CLOCK_667MHz: fsb_mhz = 667; break; } unsigned int clock = 256000 / tCKmin; @@ -1666,20 +1666,20 @@ tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); tmp |= (1 << 27); switch (ddr_clock) { - case MEM_CLOCK_667MT: - tmp |= (1 << 16) | (4 << 20); - break; - case MEM_CLOCK_800MT: - tmp |= (2 << 16) | (3 << 20); - break; - case MEM_CLOCK_1067MT: - if (!sff) - tmp |= (2 << 16) | (1 << 20); - else - tmp |= (2 << 16) | (2 << 20); - break; - default: - die("Wrong clock"); + case MEM_CLOCK_667MT: + tmp |= (1 << 16) | (4 << 20); + break; + case MEM_CLOCK_800MT: + tmp |= (2 << 16) | (3 << 20); + break; + case MEM_CLOCK_1067MT: + if (!sff) + tmp |= (2 << 16) | (1 << 20); + else + tmp |= (2 << 16) | (2 << 20); + break; + default: + die("Wrong clock"); } mchbar_write32(addr, tmp); } @@ -1707,15 +1707,15 @@ (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); tmp |= (1<<7) | (1<<11) | (1<<16); switch (ddr3clock) { - case MEM_CLOCK_667MT: - tmp |= 9 << 28; - break; - case MEM_CLOCK_800MT: - tmp |= 7 << 28; - break; - case MEM_CLOCK_1067MT: - tmp |= 8 << 28; - break; + case MEM_CLOCK_667MT: + tmp |= 9 << 28; + break; + case MEM_CLOCK_800MT: + tmp |= 7 << 28; + break; + case MEM_CLOCK_1067MT: + tmp |= 8 << 28; + break; } mchbar_write32(0x140c, tmp); @@ -1725,15 +1725,15 @@ tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); tmp |= (3<<11); switch (ddr3clock) { - case MEM_CLOCK_667MT: - tmp |= (2 << 24) | (10 << 16); - break; - case MEM_CLOCK_800MT: - tmp |= (3 << 24) | (7 << 16); - break; - case MEM_CLOCK_1067MT: - tmp |= (4 << 24) | (4 << 16); - break; + case MEM_CLOCK_667MT: + tmp |= (2 << 24) | (10 << 16); + break; + case MEM_CLOCK_800MT: + tmp |= (3 << 24) | (7 << 16); + break; + case MEM_CLOCK_1067MT: + tmp |= (4 << 24) | (4 << 16); + break; } mchbar_write32(0x1414, tmp); @@ -1747,15 +1747,15 @@ tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); tmp |= (0x3 << 20) | (5 << 24); switch (ddr3clock) { - case MEM_CLOCK_667MT: - tmp |= (2 << 8) | 0xc; - break; - case MEM_CLOCK_800MT: - tmp |= (3 << 8) | 0xa; - break; - case MEM_CLOCK_1067MT: - tmp |= (4 << 8) | 0x7; - break; + case MEM_CLOCK_667MT: + tmp |= (2 << 8) | 0xc; + break; + case MEM_CLOCK_800MT: + tmp |= (3 << 8) | 0xa; + break; + case MEM_CLOCK_1067MT: + tmp |= (4 << 8) | 0x7; + break; } mchbar_write32(0x142c, tmp); diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 3be674a..5264d48 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -160,15 +160,15 @@ } switch (sysinfo->selected_timings.fsb_clock) { - case FSB_CLOCK_667MHz: - mchbar_write32(0x11d0, 0x0fd88000); - break; - case FSB_CLOCK_800MHz: - mchbar_write32(0x11d0, 0x1303c000); - break; - case FSB_CLOCK_1067MHz: - mchbar_write32(0x11d0, 0x194a0000); - break; + case FSB_CLOCK_667MHz: + mchbar_write32(0x11d0, 0x0fd88000); + break; + case FSB_CLOCK_800MHz: + mchbar_write32(0x11d0, 0x1303c000); + break; + case FSB_CLOCK_1067MHz: + mchbar_write32(0x11d0, 0x194a0000); + break; } tmp = mchbar_read32(0x11d4) & ~0x1f; mchbar_write32(0x11d4, tmp | 4); diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 9e3708a..421c561 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -10,10 +10,10 @@ static uint32_t encode_pciexbar_length(void) { switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { - case 256: return 0 << 1; - case 128: return 1 << 1; - case 64: return 2 << 1; - default: return dead_code_t(uint32_t); + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/79444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d Gerrit-Change-Number: 79444 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 USDT port
by Riku Viitanen (Code Review) 23 Dec '23

23 Dec '23

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79745?usp=email ) Change subject: mb/hp: Add Compaq Elite 8300 USDT port ...................................................................... mb/hp: Add Compaq Elite 8300 USDT port Currently untested. Based on autoport and Z220 superio configuration. Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/hp/compaq_elite_8300_cmt/Kconfig A src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name A src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc A src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c A src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt A src/mainboard/hp/compaq_elite_8300_cmt/cmos.default A src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout A src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb A src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl A src/mainboard/hp/compaq_elite_8300_cmt/early_init.c A src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads A src/mainboard/hp/compaq_elite_8300_cmt/gpio.c A src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c A src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c 17 files changed, 655 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/79745/1 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig new file mode 100644 index 0000000..d3a5c3b --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig @@ -0,0 +1,38 @@ +if BOARD_HP_COMPAQ_ELITE_8300_CMT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_INT15 + select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NPCD378 + select USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x570000 + +config MAINBOARD_DIR + default "hp/compaq_elite_8300_cmt" + +config MAINBOARD_PART_NUMBER + default "HP Compaq Elite 8300 CMT" + +config VGA_BIOS_ID + default "8086,0152" + +config DRAM_RESET_GATE_GPIO + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + default 2 +endif diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name new file mode 100644 index 0000000..bd399b1 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_COMPAQ_ELITE_8300_CMT + bool "Compaq Elite 8300 CMT" diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc new file mode 100644 index 0000000..fb492d3 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl new file mode 100644 index 0000000..73fa78e --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl new file mode 100644 index 0000000..54f8e3f --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */ + +#include <superio/nuvoton/npcd378/acpi/superio.asl> + +Scope (\_GPE) +{ + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + //FIXME: Add GBE device + //Notify (\_SB.PCI0.GBE, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + } +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c new file mode 100644 index 0000000..8f4f83b --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt new file mode 100644 index 0000000..16c29e8 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default new file mode 100644 index 0000000..6d27a79 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M +psu_fan_lvl=3 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout new file mode 100644 index 0000000..1fc83b1 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout @@ -0,0 +1,74 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +400 3 h 0 psu_fan_lvl + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +448 128 r 0 vbnv + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb new file mode 100644 index 0000000..dc33e98 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + # BTX mainboard: Reversed mapping + register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" + device domain 0 on + subsystemid 0x103c 0x3396 inherit + + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc0801" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci1 on end # USB2 EHCI #1 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref sata1 on end # SATA Controller 1 + device ref sata2 off end # SATA Controller 2 + device ref smbus on end # SMBus + + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 off end + device ref pcie_rp5 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + + device ref pci_bridge on end + device ref lpc on # LPC bridge + chip superio/common # copied from Z220 + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + + # serialice: Vendor writes: + irq 0x14 = 0x9c + irq 0x1c = 0xa8 + irq 0x1d = 0x08 + irq 0x22 = 0x3f + irq 0x1a = 0xb0 + # dumped from superiotool: + irq 0x1b = 0x1e + irq 0x27 = 0x08 + irq 0x2a = 0x20 + irq 0x2d = 0x01 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 0x07 + drq 0x74 = 0x01 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x620 + end + device pnp 2e.8 on # HWM + io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector + + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 + + drq 0xf4 = 0x66 + drq 0xf5 = 0x67 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x08 + drq 0xfe = 0x80 + end + device pnp 2e.15 on # BUS ? + io 0x60 = 0x0680 + io 0x62 = 0x0690 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e on # GPIO ? + io 0x60 = 0x660 + drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end + end + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end + end + end +end diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl new file mode 100644 index 0000000..e8e2b3a --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c new file mode 100644 index 0000000..ae75d7c --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/nuvoton/npcd378/npcd378.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads new file mode 100644 index 0000000..90424a9 --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c new file mode 100644 index 0000000..2ae852a --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c new file mode 100644 index 0000000..a1eafcd --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c3396, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c3396), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0, 0x1d, 0x415901f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c new file mode 100644 index 0000000..8dbd95e --- /dev/null +++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79625?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p ...................................................................... mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p Extracted from a system running OEM BIOS version F.42. intelvbttool --inlegacy --outvbt data.vbt Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79625 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/hp/snb_ivb_laptops/Kconfig A src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 2ef8956..f0bd55f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -54,6 +54,7 @@ select BOARD_HP_SNB_IVB_LAPTOPS_COMMON select BOARD_ROMSIZE_KB_8192 select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt new file mode 100644 index 0000000..61d6949 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/79625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Gerrit-Change-Number: 79625 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: .gitreview: Update default branch from master to main
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79743?usp=email ) Change subject: .gitreview: Update default branch from master to main ...................................................................... .gitreview: Update default branch from master to main The master is deprecated in favor of the main. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79743 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M .gitreview 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/.gitreview b/.gitreview index 20191c7..5d4fcd8 100644 --- a/.gitreview +++ b/.gitreview @@ -2,4 +2,4 @@ host=review.coreboot.org port=29418 project=coreboot -defaultbranch=master +defaultbranch=main -- To view, visit https://review.coreboot.org/c/coreboot/+/79743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Gerrit-Change-Number: 79743 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Honor POST code Kconfig option
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79725?usp=email ) Change subject: sb/intel/bd82x6x: Honor POST code Kconfig option ...................................................................... sb/intel/bd82x6x: Honor POST code Kconfig option This southbridge can route POST codes written to port 0x80 to either LPC or PCI, but currently always route them to LPC. Change it so that POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is selected, LPC otherwise. Rename the static function because POST codes no longer always go to LPC. Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/bootblock.c 1 file changed, 7 insertions(+), 4 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..3260021 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -5,10 +5,13 @@ #include <southbridge/intel/common/early_spi.h> #include "pch.h" -static void enable_port80_on_lpc(void) +static void setup_port80(void) { - /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); + /* Enable port 80 POST */ + if (CONFIG(POST_DEVICE_PCI_PCIE)) + RCBA32(GCS) |= 0x04; /* ... on PCI(e) */ + else + RCBA32(GCS) &= (~0x04); /* ... on LPC */ } static void set_spi_speed(void) @@ -37,7 +40,7 @@ early_pch_init(); - enable_port80_on_lpc(); + setup_port80(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Gerrit-Change-Number: 79725 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Update DTT settings for thermal control
by Paul Menzel (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Kun Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79683?usp=email ) Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79683/comment/410d9efa_cc4216e8 : PS3, Line 7: Update DTT settings for thermal control Please be more specific next time. https://review.coreboot.org/c/coreboot/+/79683/comment/14d62496_2a4ff6a9 : PS3, Line 9: update DTT settings for thermal control,the values before : Sensor1 and Sensor2 were set too high. Modify the protection : temperature to better meet DUT requirements. Please use 72 characters per line, and add a space after a comma. -- To view, visit https://review.coreboot.org/c/coreboot/+/79683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Gerrit-Change-Number: 79683 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sat, 23 Dec 2023 13:42:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Update DTT settings for thermal control
by Subrata Banik (Code Review) 23 Dec '23

23 Dec '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79683?usp=email ) Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control ...................................................................... mb/google/rex/var/screebo: Update DTT settings for thermal control update DTT settings for thermal control,the values before Sensor1 and Sensor2 were set too high. Modify the protection temperature to better meet DUT requirements. BUG=b:291217859 BRANCH=none TEST=emerge-rex coreboot Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683 Reviewed-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Rui Zhou: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 3b62e02..83366ae 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -224,8 +224,8 @@ # TODO: below values are initial reference values only register "policies.critical" = "{ [0] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 70, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), }" ## Power Limits Control -- To view, visit https://review.coreboot.org/c/coreboot/+/79683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Gerrit-Change-Number: 79683 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p
by Riku Viitanen (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Paul Menzel. Riku Viitanen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79625?usp=email ) Change subject: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79625/comment/99d7ba15_b8345e1b : PS1, Line 9: OEM BIOS > Please add the version. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Gerrit-Change-Number: 79625 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 23 Dec 2023 10:53:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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