coreboot-gerrit December 2023

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[S] Change in coreboot[main]: superio/fintek/f71808a: Add VT2 boundary registers
by Martin L Roth (Code Review) 25 Dec '23

25 Dec '23

Attention is currently required from: Angel Pons, Felix Held, Ravi Mistry. Martin L Roth has uploaded a new patch set (#4) to the change originally created by Ravi Mistry. ( https://review.coreboot.org/c/coreboot/+/62200?usp=email ) Change subject: superio/fintek/f71808a: Add VT2 boundary registers ...................................................................... superio/fintek/f71808a: Add VT2 boundary registers This patch adds support for VT2 boundary registers on F71808A. These are used to set temperatures at which the speed of fan 2 changes (for fan curves). Tested on a HP 500-319na (Memphis-S / IPM87-MP). Code is almost identical to fintek/f81866d. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: https://web.archive.org/web/20160627091046/http://www.alldatasheet.com/data… Signed-off-by: Ravi Mistry <rvstry(a)protonmail.com> Change-Id: I2f6b50da073cb55e141d6bf5185433c21d3fb554 --- M src/superio/fintek/f71808a/chip.h M src/superio/fintek/f71808a/f71808a_hwm.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62200/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f6b50da073cb55e141d6bf5185433c21d3fb554 Gerrit-Change-Number: 62200 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ravi Mistry Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ravi Mistry Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: superio/fintek/f71808a/f71808a_hwm.c: Fix writing to hardware monitor...
by Martin L Roth (Code Review) 25 Dec '23

25 Dec '23

Attention is currently required from: Felix Held, Ravi Mistry. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69260?usp=email ) Change subject: superio/fintek/f71808a/f71808a_hwm.c: Fix writing to hardware monitor registers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13e91e9900cfd151d143af4530d18ece2dbbe647 Gerrit-Change-Number: 69260 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ravi Mistry Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ravi Mistry Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 25 Dec 2023 03:13:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/fintek/f71808a: Add VT2 boundary registers
by Martin L Roth (Code Review) 25 Dec '23

25 Dec '23

Attention is currently required from: Angel Pons, Felix Held, Ravi Mistry. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62200?usp=email ) Change subject: superio/fintek/f71808a: Add VT2 boundary registers ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62200/comment/0a6ff729_237dd0da : PS3, Line 17: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html > How would one do it? Go to archive.org and past in the url. If it's already been collected, just go look for a date that you like and grab the url. If it hasn't been collected, submit it for collection, then grab the archive.org URL. https://web.archive.org/web/20160627091046/http://www.alldatasheet.com/data… -- To view, visit https://review.coreboot.org/c/coreboot/+/62200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f6b50da073cb55e141d6bf5185433c21d3fb554 Gerrit-Change-Number: 62200 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ravi Mistry Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ravi Mistry Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 25 Dec 2023 03:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 CMT port
by Riku Viitanen (Code Review) 24 Dec '23

24 Dec '23

Riku Viitanen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79745?usp=email ) Change subject: mb/hp: Add Compaq Elite 8300 CMT port ...................................................................... Patch Set 10: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 10 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2023 16:54:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: SoC independent domain and host bridge resource in...
by Nico Huber (Code Review) 24 Dec '23

24 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79656?usp=email ) Change subject: soc/intel/xeon_sp: SoC independent domain and host bridge resource interface ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: We actually talked a bit about how to get new things upstream in the last leadership meeting [1]. When new code is written downstream without discussing it before, risks are generally high that it won't get accepted in the original downstream state. > the SoC codes could choose the simplest path to integrate as long as the design is decent This seems highly subjective. From my point of view the simplest path is often to re-use as much generic code as possible. And a decent design wouldn't re-invent any wheel in soc-specific code. As I mentioned elsewhere, we try to keep coreboot maintained as a whole with all the support for the different platforms in our tree. This requires tree-wide refactorings from time to time. For instance CB:78328, the only thing that has been holding it back for the past half year is the xeon_sp code. Because somebody re-invented things in xeon_sp code. If there's any sign that this could happen again with new patches, you risk to have a hard time during review. In a way, using the flexibility you mentioned can make coreboot inflexible as a whole. And that needs to be avoided. We'll have to see if that's a concern for your new code. Just want to make it understandable why a review sometimes doesn't turn out well. [1] Scroll down to ### [PatrickG, Martin] How to present design proposals? https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/3YT… -- To view, visit https://review.coreboot.org/c/coreboot/+/79656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idaac7b908fd607ff0edb8f91515cabf8c7be366f Gerrit-Change-Number: 79656 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 24 Dec 2023 12:12:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 24 Dec '23

24 Dec '23

Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40300?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: I've pushed a new version of this to CB:79746. -- To view, visit https://review.coreboot.org/c/coreboot/+/40300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 6 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 24 Dec 2023 10:45:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data
by Keith Hui (Code Review) 24 Dec '23

24 Dec '23

Attention is currently required from: Angel Pons. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78206?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data ...................................................................... [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data Portions of MRC raminit code only serves to enter fixed constants into pei_data structure for MRC consumption. Since the constants are all to the front of the structure, set up a truncated copy for compiler to render at build time. Chipset code then uses it as a base to initialize the (in-CAR) structure and fill out the rest at runtime. TEST=No regression observed when booting on asus/p8z77-m. Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 40 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78206/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Gerrit-Change-Number: 78206 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800
by Keith Hui (Code Review) 24 Dec '23

24 Dec '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79726?usp=email ) Change subject: mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800 ...................................................................... mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800 The setting was reduced to 666 for native raminit in commit 7039edd2da30 (SNB+MRC boards: Migrate MRC settings to devicetree) based on boot test results at the time. With more changes merged, additional native raminit tests were done on p8z77-m. It is now possible for previously failing memory configurations to operate at full speed. This, combined with multiple reports on gerrit that this family does work at 800, warrants returning the setting to what it was. Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/79726/1 diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index cd4336f..6a18b01 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -4,8 +4,7 @@ # All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported # DIMMs down to 1.25v register "ddr3lv_support" = "1" - # FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem - register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" + register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" register "usb_port_config" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/79726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Gerrit-Change-Number: 79726 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 24 Dec '23

24 Dec '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79746?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots to Arch Linux (Linux 6.6.3) from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/dell/e7240.md M Documentation/mainboard/index.md A src/mainboard/dell/e7240/Kconfig A src/mainboard/dell/e7240/Kconfig.name A src/mainboard/dell/e7240/Makefile.inc A src/mainboard/dell/e7240/acpi/ec.asl A src/mainboard/dell/e7240/acpi/platform.asl A src/mainboard/dell/e7240/acpi/superio.asl A src/mainboard/dell/e7240/board_info.txt A src/mainboard/dell/e7240/bootblock.c A src/mainboard/dell/e7240/devicetree.cb A src/mainboard/dell/e7240/dsdt.asl A src/mainboard/dell/e7240/gma-mainboard.ads A src/mainboard/dell/e7240/gpio.c A src/mainboard/dell/e7240/hda_verb.c A src/mainboard/dell/e7240/romstage.c 16 files changed, 471 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79746/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 24 Dec '23

24 Dec '23

Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This is a rework of CB:40300 based on the latest code. I don't know why gerrit doesn't use CB:40300 while the Change-Id doesn't change. I reuse ec/dell/mec5035, but it doesn't boot when I use it in the devicetree, so the touchpad still doesn't work. -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Sun, 24 Dec 2023 03:09:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2023