coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
by Subrata Banik (Code Review) 02 Dec '23

02 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Stefan Reinauer, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79332?usp=email to look at the new patch set (#5). Change subject: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 ...................................................................... mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID which is identical to MCH ID 0x7d01 (index 1). TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79332/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Gerrit-Change-Number: 79332 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Felix Held (Code Review) 02 Dec '23

02 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79365?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Update amd_blobs submodule to upstream main branch Updating from commit id eb91266f01db (2023-11-29): MDN: Update mendocino SMU to 90.43.0 to commit id 64cdd7c8ef19 (2023-12-01): Cezanne/PSP: clean up release notes This brings in 3 new commits: 64cdd7c8ef Cezanne/PSP: clean up release notes 54c45443b8 Stoneyridge: Drop PSP binaries for Bristol Ridge (BR) bfa3c44c8c Stoneyridge: Tidy up the PSP binaries folder Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79365 Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Varshit Pandya: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index eb91266..64cdd7c 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit eb91266f01db2d276614dc20d8d0f857e6ffbf00 +Subproject commit 64cdd7c8ef199f5d79be14e7972fb7316f41beed -- To view, visit https://review.coreboot.org/c/coreboot/+/79365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8 Gerrit-Change-Number: 79365 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Felix Held (Code Review) 02 Dec '23

02 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... soc/amd: Add DBG2 ACPI table Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/common/block/acpi/tables.c 3 files changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 17cd24c..942d464 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -896,6 +896,14 @@ name); } +unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, + uint64_t base, const char *name) +{ + return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base, + 0x100, ACPI_ACCESS_SIZE_DWORD_ACCESS, + name); +} + static void acpi_create_facs(void *header) { acpi_facs_t *facs = header; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index a26d735..0941dee 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1659,6 +1659,8 @@ const struct device *dev, uint8_t access_size); unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, uint64_t base, const char *name); +unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, + uint64_t base, const char *name); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index bda283a..d49d307 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -4,11 +4,18 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <device/device.h> +#include <console/uart.h> #include <types.h> unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + current = acpi_16550_mmio32_write_dbg2_uart(rsdp, current, + uart_platform_base(get_uart_for_console()), NULL); + + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype
by Felix Held (Code Review) 02 Dec '23

02 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79219?usp=email ) Change subject: acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype ...................................................................... acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79219 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 9a9a66d..a26d735 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -866,12 +866,13 @@ _Static_assert(sizeof(acpi_madt_gic_its_t) == 20, "Wrong MADT acpi_madt_gic_its_t size\n"); #define ACPI_DBG2_PORT_SERIAL 0x8000 -#define ACPI_DBG2_PORT_SERIAL_16550 0x0000 +#define ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY 0x0000 #define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001 #define ACPI_DBG2_PORT_SERIAL_ARM_PL011 0x0003 #define ACPI_DBG2_PORT_SERIAL_ARM_SBSA 0x000e #define ACPI_DBG2_PORT_SERIAL_ARM_DDC 0x000f #define ACPI_DBG2_PORT_SERIAL_BCM2835 0x0010 +#define ACPI_DBG2_PORT_SERIAL_16550 0x0012 #define ACPI_DBG2_PORT_IEEE1394 0x8001 #define ACPI_DBG2_PORT_IEEE1394_STANDARD 0x0000 #define ACPI_DBG2_PORT_USB 0x8002 -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
by Paul Menzel (Code Review) 02 Dec '23

02 Dec '23

Attention is currently required from: Weimin Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79166?usp=email ) Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power. ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79166/comment/21a1909c_3d1391a4 : PS8, Line 6: > Didn't we have a linter for that? See above, it’s a checkpatch comment. Linter comments are marked as Resolved by default though. -- To view, visit https://review.coreboot.org/c/coreboot/+/79166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Gerrit-Change-Number: 79166 Gerrit-PatchSet: 9 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sat, 02 Dec 2023 17:33:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Nico Huber (Code Review) 02 Dec '23

02 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (5 comments) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/78327/comment/dd8d0d56_00b3159c : PS4, Line 591: static void host_bridge_resources(struct device *dev) Nit, the other function names around are much more verbose, e.g. this could be `pci_host_bridge_read_resources()`. https://review.coreboot.org/c/coreboot/+/78327/comment/0d9f10aa_d5609028 : PS4, Line 617: uint16_t For PCI this is always limited to 255, i.e. `uint8_t`, isn't it? I'm actually not sure about PCIe extensions... Also, shouldn't we set the `max_subordinate` here, i.e. where the bus window for this host bridge ends? Does the caller know it? File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/78327/comment/60d78db3_19871714 : PS4, Line 17: const IIO_UDS *hob = get_iio_uds(); Could be NULL https://review.coreboot.org/c/coreboot/+/78327/comment/cfce9eec_abb862dc : PS4, Line 18: MAX_IIO_STACK Here comes the fun: SKX uses MAX_IIO_STACK to size this, but CPX on use MAX_LOGIC_IIO_STACK. I'm not sure what is the right thing to do here. The current effect seems to be that we skip 2 stack entries from the HOB per node. Is this intended? If we change this, the setting `path.domain.domain` below needs to be adjusted as well. https://review.coreboot.org/c/coreboot/+/78327/comment/04d4a93f_31e4b15c : PS4, Line 99: host_bridge->link_list->max_subordinate = i; Could me make this an additional parameter to alloc_pci_host_bridge()? -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 02 Dec 2023 16:06:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/docker/alma: Add Dockerfile.base
by Felix Singer (Code Review) 02 Dec '23

02 Dec '23

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79389?usp=email ) Change subject: util/docker/alma: Add Dockerfile.base ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79389?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab15fe908aa6ca81724ed7557caf70c38817ad25 Gerrit-Change-Number: 79389 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2023 09:27:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
by Felix Singer (Code Review) 02 Dec '23

02 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78628?usp=email ) Change subject: inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header ...................................................................... inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header Inteltool is GPLv2 licensed so all files that link to it should be GPLv2 by default. In addition, the contents of several of these headers were originally moved directly from gpio_groups.c, which is explicitly marked as GPL-2.0-only. Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/inteltool/gpio_names/alderlake_h.h M util/inteltool/gpio_names/alderlake_p.h M util/inteltool/gpio_names/apollolake.h M util/inteltool/gpio_names/cannonlake.h M util/inteltool/gpio_names/cannonlake_lp.h M util/inteltool/gpio_names/denverton.h M util/inteltool/gpio_names/elkhartlake.h M util/inteltool/gpio_names/emmitsburg.h M util/inteltool/gpio_names/geminilake.h M util/inteltool/gpio_names/gpio_groups.h M util/inteltool/gpio_names/icelake.h M util/inteltool/gpio_names/jasperlake.h M util/inteltool/gpio_names/lewisburg.h M util/inteltool/gpio_names/sunrise.h M util/inteltool/gpio_names/tigerlake.h 15 files changed, 30 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/inteltool/gpio_names/alderlake_h.h b/util/inteltool/gpio_names/alderlake_h.h index d3a9ed6..0bd0151 100644 --- a/util/inteltool/gpio_names/alderlake_h.h +++ b/util/inteltool/gpio_names/alderlake_h.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_ALDERLAKE_H #define GPIO_NAMES_ALDERLAKE_H diff --git a/util/inteltool/gpio_names/alderlake_p.h b/util/inteltool/gpio_names/alderlake_p.h index 79d5ce7..2bd5fed 100644 --- a/util/inteltool/gpio_names/alderlake_p.h +++ b/util/inteltool/gpio_names/alderlake_p.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_ALDERLAKE_P #define GPIO_NAMES_ALDERLAKE_P diff --git a/util/inteltool/gpio_names/apollolake.h b/util/inteltool/gpio_names/apollolake.h index ec4a934..83ddd52 100644 --- a/util/inteltool/gpio_names/apollolake.h +++ b/util/inteltool/gpio_names/apollolake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_APOLLOLAKE_H #define GPIO_NAMES_APOLLOLAKE_H diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 694b158..aaaf2ad 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_CANNONLAKE_H #define GPIO_NAMES_CANNONLAKE_H diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index af14c1f..38b24e4 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_CANNONLAKE_LP #define GPIO_NAMES_CANNONLAKE_LP diff --git a/util/inteltool/gpio_names/denverton.h b/util/inteltool/gpio_names/denverton.h index 8c56cd2..1ab2f26 100644 --- a/util/inteltool/gpio_names/denverton.h +++ b/util/inteltool/gpio_names/denverton.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_DENVERTON_H #define GPIO_NAMES_DENVERTON_H diff --git a/util/inteltool/gpio_names/elkhartlake.h b/util/inteltool/gpio_names/elkhartlake.h index 3d9a3c3..75d65d3 100644 --- a/util/inteltool/gpio_names/elkhartlake.h +++ b/util/inteltool/gpio_names/elkhartlake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_ELKHARTLAKE #define GPIO_NAMES_ELKHARTLAKE diff --git a/util/inteltool/gpio_names/emmitsburg.h b/util/inteltool/gpio_names/emmitsburg.h index 382a080..8522396 100644 --- a/util/inteltool/gpio_names/emmitsburg.h +++ b/util/inteltool/gpio_names/emmitsburg.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_EMMITSBURG_H #define GPIO_NAMES_EMMITSBURG_H diff --git a/util/inteltool/gpio_names/geminilake.h b/util/inteltool/gpio_names/geminilake.h index e918b0f..eed0509 100644 --- a/util/inteltool/gpio_names/geminilake.h +++ b/util/inteltool/gpio_names/geminilake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_GEMINILAKE_H #define GPIO_NAMES_GEMINILAKE_H diff --git a/util/inteltool/gpio_names/gpio_groups.h b/util/inteltool/gpio_names/gpio_groups.h index 9ae2a8f..828d2fd 100644 --- a/util/inteltool/gpio_names/gpio_groups.h +++ b/util/inteltool/gpio_names/gpio_groups.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_GPIO_GROUPS_H #define GPIO_NAMES_GPIO_GROUPS_H diff --git a/util/inteltool/gpio_names/icelake.h b/util/inteltool/gpio_names/icelake.h index 48b8431..95636d4 100644 --- a/util/inteltool/gpio_names/icelake.h +++ b/util/inteltool/gpio_names/icelake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_ICELAKE_H #define GPIO_NAMES_ICELAKE_H diff --git a/util/inteltool/gpio_names/jasperlake.h b/util/inteltool/gpio_names/jasperlake.h index f6c1dc6..81a6674 100644 --- a/util/inteltool/gpio_names/jasperlake.h +++ b/util/inteltool/gpio_names/jasperlake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_JASPERLAKE #define GPIO_NAMES_JASPERLAKE diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h index e963cc0..a089d37 100644 --- a/util/inteltool/gpio_names/lewisburg.h +++ b/util/inteltool/gpio_names/lewisburg.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_LEWISBURG_H #define GPIO_NAMES_LEWISBURG_H diff --git a/util/inteltool/gpio_names/sunrise.h b/util/inteltool/gpio_names/sunrise.h index 6a47556..310742d 100644 --- a/util/inteltool/gpio_names/sunrise.h +++ b/util/inteltool/gpio_names/sunrise.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_SUNRISE_H #define GPIO_NAMES_SUNRISE_H diff --git a/util/inteltool/gpio_names/tigerlake.h b/util/inteltool/gpio_names/tigerlake.h index c1b1b85..ac5ee43 100644 --- a/util/inteltool/gpio_names/tigerlake.h +++ b/util/inteltool/gpio_names/tigerlake.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef GPIO_NAMES_TIGERLAKE_LP #define GPIO_NAMES_TIGERLAKE_LP -- To view, visit https://review.coreboot.org/c/coreboot/+/78628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a Gerrit-Change-Number: 78628 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expecta...
by Sukumar Ghorai (Code Review) 02 Dec '23

02 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79386?usp=email ) Change subject: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79386/comment/07147191_6d97fb4b : PS3, Line 9: which is deemed insufficiently : aggressive for meeting the MTL performance expectations in : balance_performance mode. > EPP=45% is giving the required performance with very minimum power impact. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/79386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Gerrit-Change-Number: 79386 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Dec 2023 08:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expecta...
by Sukumar Ghorai (Code Review) 02 Dec '23

02 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79386?usp=email to look at the new patch set (#4). Change subject: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation ...................................................................... mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation The default EPP is set at 50%, which is deemed insufficiently aggressive for meeting the MTL performance expectations in balance_performance mode. # cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference balance_performance # iotools rdmsr 0 0x774 0x0000000080003f06 EPP=45% is giving the required performance in MTL. # iotools rdmsr 0 0x774 0x0000000073003d06 BUG=b:314275133 TEST=Build and boot Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79386/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Gerrit-Change-Number: 79386 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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