Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79166?usp=email )
Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79166/comment/36c0506b_36c5f238 :
PS8, Line 6:
> See above, it’s a checkpatch comment. Linter comments are marked as Resolved by default though.
Acknowledged
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 30:
(6 comments)
File src/mainboard/dell/optiplex_9020/Kconfig:
https://review.coreboot.org/c/coreboot/+/55232/comment/f61388b9_6f967d4c :
PS30, Line 22: hex
Symbol type is not necessary as it is defined in the src/Kconfig
https://review.coreboot.org/c/coreboot/+/55232/comment/a634d5dd_b39cf7ec :
PS30, Line 26: string
Symbol type not necessary
https://review.coreboot.org/c/coreboot/+/55232/comment/9c300dfa_497a9afa :
PS30, Line 30: string
Symbol type not necessary
File src/mainboard/dell/optiplex_9020/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/25d850b9_96ab9835 :
PS30, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
Should be
```
/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */
```
for otherwise empty files. Refer to commit cf4722d317
File src/mainboard/dell/optiplex_9020/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/2d9e0561_c0024a24 :
PS30, Line 1: GPL-2.0-only
CC-PDDC, see my comment on ec.asl
File src/mainboard/dell/optiplex_9020/overridetree_mt.cb:
https://review.coreboot.org/c/coreboot/+/55232/comment/86ea1225_a37b605c :
PS30, Line 6: birdge
bridge
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Change subject: util/docker/fedora: Add Dockerfile.base
......................................................................
Patch Set 5:
(2 comments)
This change is ready for review.
Patchset:
PS1:
> Build-tests missing
Done
File util/docker/fedora/Dockerfile.base:
https://review.coreboot.org/c/coreboot/+/79316/comment/062df6d0_3415af0a :
PS5, Line 40: \
> To minimize the docker image size, maybe clean the caches? […]
Oh right. thanks. yum doesn't exist anymore, I will leave the dnf directory.
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Change subject: lib/smbios: Add 32 bit entry point if below 4G
......................................................................
Patch Set 1:
(1 comment)
File src/lib/smbios.c:
https://review.coreboot.org/c/coreboot/+/76911/comment/b8dee122_98367ed9 :
PS1, Line 1215: if (current < UINT32_MAX) {
> > I think for now they're always going to be below 4GiB, so I don't think this check is even needed […]
I will mark it as resolved since this is something for another patch.
Although looking at this code again after some time I feel like I would still like to keep the comment even if I would use your suggested function.
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Hello Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: util/ifdtool/ifdtool.c: Add validation exception
......................................................................
util/ifdtool/ifdtool.c: Add validation exception
When validating the FMAP against the IFD, the BIOS region is a somewhat
specical case, since the FMAP BIOS region usually does not match the IFD
BIOS region. Instead the FMAP region usually resides somewhere inside
the IFD BIOS region and the where depends on CONFIG_CBFS_SIZE.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d
---
M util/ifdtool/ifdtool.c
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79368/2
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Change subject: util/ifdtool/ifdtool.c: Add validation exception
......................................................................
util/ifdtool/ifdtool.c: Add validation exception
When validating the FMAP against the IFD, the BIOS region is a somewhat
specical case, since the FMAP BIOS region usually does not match the IFD
BIOS region. Instead the FMAP region usually resides somewhere inside
the IFD BIOS region and the where depends on CONFIG_CBFS_SIZE.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d
---
M util/ifdtool/ifdtool.c
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79368/1
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 43451b1..f799729 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1181,6 +1181,19 @@
matches++; // found a match between FMAP and IFD region
if ((uint)region.base != area->offset || (uint)region.size != area->size) {
+ if (i == REGION_BIOS) {
+ /*
+ * BIOS FMAP region is a special case
+ * Coreboots FMAP BIOS region depends on the CONFIG_CBFS_SIZE
+ * while the IFD BIOS region is always of static size.
+ * Therefore we just make sure that the BIOS region of the FMAP
+ * is inside the region specified by the IFD
+ */
+ if ((uint)region.base <= area->offset &&
+ ((uint)region.base + region.size) >= (area->offset + area->size)) {
+ continue;
+ }
+ }
printf("Region mismatch between %s and %s\n", region_names[i].terse, area->name);
printf(" Descriptor region %s:\n", region_names[i].terse);
printf(" offset: 0x%08x\n", region.base);
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I'd like you to reexamine a change. Please visit
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Change subject: treewide: Move stdlib.h to commonlib
......................................................................
treewide: Move stdlib.h to commonlib
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since
all code is BSD licensed anyway.
It also moves some code from libpayloads stdlib.h to
commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is
useful for a subsequent commit that adds devicetree.c into commonlib.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a
---
M Makefile.inc
M payloads/libpayload/include/stdlib.h
M src/arch/x86/Makefile.inc
A src/arch/x86/dma.c
R src/commonlib/bsd/include/commonlib/bsd/stdlib.h
M src/commonlib/storage/bouncebuf.c
M src/commonlib/storage/sdhci.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/include/stdlib.h
M src/lib/device_tree.c
M src/lib/fit.c
M src/soc/intel/xeon_sp/spr/numa.c
M src/soc/mediatek/common/pcie.c
M src/soc/mediatek/mt8195/pcie.c
14 files changed, 30 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/77969/10
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Change subject: ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/rex/var/screebo: Override power limits
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79330/comment/7e168257_40801c92 :
PS3, Line 21: [INFO ] Overriding power limits PL1 (mW) (10000, 15000)
: PL2 (mW) (40000, 40000) PL4 (W) (84)
:
: After:
:
: [INFO ] Overriding power limits PL1 (mW) (10000, 15000)
: PL2 (mW) (40000, 40000) PL4 (W) (84)
> > Thank you for the explanation. So, the paste demonstrate that the debug line is gone?
>
> exactly the `DEBUG` line suggests that, we were using baseline default value (aka no override). And modified CL shows that we are using an overridden value from variant directory.
>
> >
> > I was confused by “This patch modifies the power limits value to enhance …” in the beginning. But no power limits are changed?
>
> updated the commit msg.
marking the commit resolve, please let me know if you think otherwise
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Change subject: ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case
......................................................................
Patch Set 1: Code-Review+1
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