coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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2354 discussions

[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/78327/comment/ccb60e41_8988a76a : PS4, Line 18: MAX_IIO_STACK > Here comes the fun: SKX uses MAX_IIO_STACK to size this, but CPX on use […] In GNR, we use MAX_LOGICAL_IIO_STACK. MAX_LOGICAL_IIO_STACK will enumerate UBOX buses but MAX_IIO_STACK will not. We use MAX_LOGICAL_IIO_STACK for 2 reasons: 1) in case UBOX is needed for some special setting needs in bootloader. 2) for simplicity reason, only one range is used instead of using both. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 11:11:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/alderlake: add pcie modphy settings
by Jamie Chen (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Kane Chen, Simon Yang. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79370?usp=email ) Change subject: soc/intel/alderlake: add pcie modphy settings ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79370?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08bb2236ac3f8fd8b5e286a9543519b9456d93c6 Gerrit-Change-Number: 79370 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 06:54:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/spi: Add ISSI IS25WP256D flash
by Maximilian Brune (Code Review) 04 Dec '23

04 Dec '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79369?usp=email ) Change subject: drivers/spi: Add ISSI IS25WP256D flash ...................................................................... drivers/spi: Add ISSI IS25WP256D flash tested: boot SiFive Hifive Unmatched board Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.inc A src/drivers/spi/issi.c M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h M src/include/spi-generic.h 6 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/79369/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 8c251d7..6d161f4 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -155,6 +155,13 @@ Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. +config SPI_FLASH_ISSI + bool + default y if SPI_FLASH_INCLUDE_ALL_DRIVERS + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by ISSI. + config SPI_FLASH_HAS_VOLATILE_GROUP bool default n diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 954eef2..97c3d63 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -30,6 +30,7 @@ $(1)-$(CONFIG_SPI_FLASH_SST) += sst.c $(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +$(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c endef $(eval $(call add_spi_stage,bootblock,_EARLY)) diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c new file mode 100644 index 0000000..90bab96 --- /dev/null +++ b/src/drivers/spi/issi.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <commonlib/helpers.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <delay.h> +#include <lib.h> + +#include "spi_flash_internal.h" + +static const struct spi_flash_part_id flash_table[] = { + { + /* IS25WP256D */ + .id[0] = 0x7019, + .nr_sectors_shift = 13, + }, +}; + +const struct spi_flash_vendor_info spi_flash_issi_vi = { + .id = VENDOR_ID_ISSI, + .page_size_shift = 8, // 256 byte page size + .sector_size_kib_shift = 2, // 4 Kbyte sector size + .match_id_mask[0] = 0xffff, + .ids = flash_table, + .nr_part_ids = ARRAY_SIZE(flash_table), + .desc = &spi_flash_pp_0x20_sector_desc, + .prot_ops = NULL, //TODO +}; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 7619f64..42952df 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -397,6 +397,9 @@ #if CONFIG(SPI_FLASH_WINBOND) &spi_flash_winbond_vi, #endif +#if CONFIG(SPI_FLASH_ISSI) + &spi_flash_issi_vi, +#endif }; #define IDCODE_LEN 5 diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 1927111..432480e 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -123,6 +123,7 @@ extern const struct spi_flash_vendor_info spi_flash_stmicro3_vi; extern const struct spi_flash_vendor_info spi_flash_stmicro4_vi; extern const struct spi_flash_vendor_info spi_flash_winbond_vi; +extern const struct spi_flash_vendor_info spi_flash_issi_vi; /* Page Programming Command Set with 0x20 Sector Erase command. */ extern const struct spi_flash_ops_descriptor spi_flash_pp_0x20_sector_desc; diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index acb22ec..aa28232 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -25,6 +25,7 @@ #define VENDOR_ID_SST 0xbf #define VENDOR_ID_STMICRO 0x20 #define VENDOR_ID_WINBOND 0xef +#define VENDOR_ID_ISSI 0x9d /* Controller-specific definitions: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79369?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c Gerrit-Change-Number: 79369 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/alderlake: Update LidStatus UPD dynamically
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79352?usp=email ) Change subject: soc/intel/alderlake: Update LidStatus UPD dynamically ...................................................................... soc/intel/alderlake: Update LidStatus UPD dynamically This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index d86d62c..4ceda50 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <bootmode.h> #include <bootsplash.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -637,7 +638,7 @@ /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); + s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); s_cfg->PavpEnable = CONFIG(PAVP); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79352?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Gerrit-Change-Number: 79352 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Ivy Jian (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Shelley Chen. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 05:30:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Ivy Jian (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79392?usp=email ) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 05:12:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Ivy Jian (Code Review) 04 Dec '23

04 Dec '23

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79392?usp=email ) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... mb/google/brox: Generate RAM IDs Add the support LP5 RAM parts for brox: DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/brox/memory/Makefile.inc M src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt M src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt 3 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79392/1 diff --git a/src/mainboard/google/brox/variants/brox/memory/Makefile.inc b/src/mainboard/google/brox/variants/brox/memory/Makefile.inc index 3b4cd12..30cd7b9 100644 --- a/src/mainboard/google/brox/variants/brox/memory/Makefile.inc +++ b/src/mainboard/google/brox/variants/brox/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt +# /tmp/go-build3467193440/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory/ src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B diff --git a/src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt index 4699178..2932012 100644 --- a/src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt +# /tmp/go-build3467193440/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory/ src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) diff --git a/src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt index cbae2e1..30f92a1 100644 --- a/src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt @@ -1 +1,3 @@ MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +MT62F1G32D4DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian, Nick Vaccaro. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... Patch Set 6: (1 comment) This change is ready for review. File src/mainboard/google/brox/variants/baseboard/brox/gpio.c: https://review.coreboot.org/c/coreboot/+/79355/comment/38de46de_05f647b9 : PS3, Line 404: const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) : { > I think that given that GPP_F9 is in the early bootblock gpio table already in the baseboard file (h […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 03:02:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
by Kun Liu (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Kun Liu, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Rui Zhou, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79320?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 ...................................................................... mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79320/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Gerrit-Change-Number: 79320 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brox: Update configuration for USB ports
by Ivy Jian (Code Review) 04 Dec '23

04 Dec '23

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79391?usp=email ) Change subject: mb/google/brox: Update configuration for USB ports ...................................................................... mb/google/brox: Update configuration for USB ports Update brox USB2/3 and TCP ports based on schematics. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/brox/overridetree.cb 2 files changed, 132 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79391/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 42bf467..1cdab83 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -22,20 +22,26 @@ # Enable CNVi BT register "cnvi_bt_core" = "true" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 SD bridge + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # DCI + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3 Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3 Port - register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" - register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Typc-C Port C0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable TCP1 + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Typc-C Port C2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -144,12 +150,11 @@ }" end device ref dtt on end -# device ref tbt_pcie_rp0 off end -# device ref tbt_pcie_rp1 off end -# device ref tbt_pcie_rp2 off end -# device ref tcss_xhci on end -# device ref tcss_dma0 on end -# device ref tcss_dma1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end device ref xhci on end device ref shared_sram on end device ref cnvi_wifi on diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index a5e2217..586dd70 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -1,4 +1,113 @@ chip soc/intel/alderlake device domain 0 on + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 SD Bridge"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79391?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Gerrit-Change-Number: 79391 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2023