coreboot-gerrit December 2023

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79330?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/var/screebo: Override power limits ...................................................................... mb/google/rex/var/screebo: Override power limits This patch allows variants to override the default baseboard PLx limits. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/screebo/variant.c 1 file changed, 65 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c index 1dd8b98..edddd43 100644 --- a/src/mainboard/google/rex/variants/screebo/variant.c +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> -#include <fw_config.h> #include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) @@ -29,3 +30,65 @@ config->tcss_aux_ori = 0x04; } } + +const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits variant_power_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; + +void variant_devtree_update(void) +{ + const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits; + size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = variant_power_efficient_limits; + limits_size = ARRAY_SIZE(variant_power_efficient_limits); + } + } + + variant_update_cpu_power_limits(limits, limits_size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Gerrit-Change-Number: 79330 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Paul Menzel, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79330?usp=email ) Change subject: mb/google/rex/var/screebo: Override power limits ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79330/comment/35a93503_49eaf1b4 : PS3, Line 21: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) : PL2 (mW) (40000, 40000) PL4 (W) (84) : : After: : : [INFO ] Overriding power limits PL1 (mW) (10000, 15000) : PL2 (mW) (40000, 40000) PL4 (W) (84) > > > Thank you for the explanation. So, the paste demonstrate that the debug line is gone? > > > > exactly the `DEBUG` line suggests that, we were using baseline default value (aka no override). And modified CL shows that we are using an overridden value from variant directory. > > > > > > > > I was confused by “This patch modifies the power limits value to enhance …” in the beginning. But no power limits are changed? > > > > updated the commit msg. > > marking the commit resolve, please let me know if you think otherwise i'm landing this CL because the tot is broken now, looks like because of out of order merge -- To view, visit https://review.coreboot.org/c/coreboot/+/79330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Gerrit-Change-Number: 79330 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 17:03:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Simplify power limit configuration usage
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79331?usp=email ) Change subject: mb/google/rex: Simplify power limit configuration usage ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: looks like u landed the patches out of order -- To view, visit https://review.coreboot.org/c/coreboot/+/79331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Gerrit-Change-Number: 79331 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Dec 2023 17:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79348?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S ...................................................................... soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79348 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/devapc.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified jason-ch chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 03e0dfd..6e47f705 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1163,7 +1163,8 @@ DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB1_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB2_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN4, NO_PROTECTION, FORBIDDEN8, + NO_PROTECTION, FORBIDDEN), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB3_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB4_S", -- To view, visit https://review.coreboot.org/c/coreboot/+/79348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Gerrit-Change-Number: 79348 Gerrit-PatchSet: 3 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Nico Huber (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/78327/comment/e261a5d1_bf3b8a6c : PS4, Line 112: .scan_bus = non_iio_pci_domain_scan_bus, > For non_iiostack_pci_domain_ops, maybe we could have similar renaming as well? Don't these integrated devices implement the upper layers of PCI (i.e. show as a PCI device to software)? Then it would be quite irritating to call them non-PCI. How about `integrated_iio_stack_...`? -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 16:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: security/vboot: Add Kconfig option to clear recovery request
by Matt DeVillier (Code Review) 04 Dec '23

04 Dec '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74343?usp=email ) Change subject: security/vboot: Add Kconfig option to clear recovery request ...................................................................... security/vboot: Add Kconfig option to clear recovery request For ChromeOS platform the recovery reason is cleared in vb2api_kernel_phase2 which is probably not called by any non-ChromeOS system. It results in the platform being stuck in recovery mode, e.g. when RW firmware verification fails. Even if the RW partition is flashed with correctly signed image, the persistent non-zero recovery reason will prevent vboot from attempting the RW partition check. Use the newly exposed vb2api_clear_recovery and VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE Kconfig option to clear the recovery reason and save it immediately to the VBNV. The idea is to let non-ChromeOS coreboot platform to clear the recovery reason when needed. TEST=Clear the recovery reason in mainboard_final function right before payload jump when RW partition is corrupted and RW partition is valid. In case it is corrupted, the platform stays in recovery mode, when valid the platform boots from RW partition. Tested on MSI PRO Z690-A DDR4. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7ffaf3e8f61a28a68c9802c184961b1b9bf9d617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74343 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/Kconfig M src/security/vboot/bootmode.c 2 files changed, 24 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 2d5b20f..9d90d1e 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -256,6 +256,15 @@ will automatically be 0 (meaning the whole MCACHE is used for RO). Do NOT change this value for vboot RW updates! +config VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + bool "Clear the recovery request at the end of ramstage" + default n + help + If this option is enabled, the recovery request will be cleared and + saved to VBNV storage at the end of ramstage. This is useful for + platforms without vboot-integrated payloads, to avoid being stuck in + the recovery mode. + config VBOOT_ENABLE_CBFS_FALLBACK bool default n diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 44149af..745af63 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -52,6 +52,21 @@ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, do_clear_recovery_mode_switch, NULL); +#if CONFIG(VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE) +static void vboot_clear_recovery_request(void *unused) +{ + struct vb2_context *ctx; + + ctx = vboot_get_context(); + vb2api_clear_recovery(ctx); + save_vbnv(ctx->nvdata); +} + +/* This has to be called before back_up_vbnv_cmos, so BS_ON_ENTRY is used here. */ +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + vboot_clear_recovery_request, NULL); +#endif + int __weak get_recovery_mode_retrain_switch(void) { return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/74343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ffaf3e8f61a28a68c9802c184961b1b9bf9d617 Gerrit-Change-Number: 74343 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: cpu/intel/model_206ax: Use macro IS_IVY_CPU
by Matt DeVillier (Code Review) 04 Dec '23

04 Dec '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79148?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/intel/model_206ax: Use macro IS_IVY_CPU ...................................................................... cpu/intel/model_206ax: Use macro IS_IVY_CPU Use existing macro instead of open coding magic numbers. No functionality change. Change-Id: If45f7f3f2b4226cedde6ff91b9848b9875f45f9f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79148 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 1568372..372989c 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -212,7 +212,7 @@ /* Secondary Plane Current Limit */ msr = rdmsr(MSR_PP1_CURRENT_CONFIG); msr.lo &= ~0x1fff; - if (cpuid_eax(1) >= 0x30600) + if (IS_IVY_CPU(cpu_get_cpuid())) msr.lo |= PP1_CURRENT_LIMIT_IVB; else msr.lo |= PP1_CURRENT_LIMIT_SNB; -- To view, visit https://review.coreboot.org/c/coreboot/+/79148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If45f7f3f2b4226cedde6ff91b9848b9875f45f9f Gerrit-Change-Number: 79148 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/rex/variants/deku: Complete USB configuration
by Matt DeVillier (Code Review) 04 Dec '23

04 Dec '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79356?usp=email ) Change subject: mb/google/rex/variants/deku: Complete USB configuration ...................................................................... mb/google/rex/variants/deku: Complete USB configuration +-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 191 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 1163292..86a015cf 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -98,6 +98,158 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + # FIXME - location need to be corrected once we have the final design + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb3_port2 on end + end + end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -105,6 +257,44 @@ device i2c 50 on end end end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + #USB2_C0 + use usb2_port2 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C1 + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C2 + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C3 + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/79356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Gerrit-Change-Number: 79356 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1005249 Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/variants/deku: Add basic DTT
by Matt DeVillier (Code Review) 04 Dec '23

04 Dec '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79353?usp=email ) Change subject: mb/google/rex/variants/deku: Add basic DTT ...................................................................... mb/google/rex/variants/deku: Add basic DTT Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 35ce9b46..1163292 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -55,6 +55,11 @@ }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + device generic 0 alias dptf_policy on end + end + end device ref pcie_rp7 on # Enable LAN1 Card PCIE 7 using clk 2 register "pcie_rp[PCH_RP(7)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/79353?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Gerrit-Change-Number: 79353 Gerrit-PatchSet: 4 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Enable LAN0, LAN1
by Matt DeVillier (Code Review) 04 Dec '23

04 Dec '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79292?usp=email ) Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1 ...................................................................... mb/google/rex/var/deku: Enable LAN0, LAN1 google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/deku/gpio.c M src/mainboard/google/rex/variants/deku/overridetree.cb 2 files changed, 32 insertions(+), 2 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index 324c236..94c06e8 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -144,7 +144,7 @@ /* GPP_D00 : net NC is not present in the given design */ PAD_NC(GPP_D00, NONE), /* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_SCI_LOW(GPP_D01, NONE, DEEP, EDGE_SINGLE), /* GPP_D02 : [] ==> LAN1_PERST_L */ PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), /* GPP_D03 : net NC is not present in the given design */ @@ -199,7 +199,7 @@ /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E04 : [] ==> LAN0_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_SCI_LOW(GPP_E04, NONE, DEEP, EDGE_SINGLE), /* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 4dca7e2..35ce9b46 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -55,6 +55,36 @@ }" device domain 0 on + device ref pcie_rp7 on + # Enable LAN1 Card PCIE 7 using clk 2 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_01" # GPP_D01 + register "device_index" = "0" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # PCIE7 LAN1 card + device ref pcie_rp10 on + # Enable LAN0 Card PCIE 10 using clk 8 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_04" # GPP_E04 + register "device_index" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # PCIE10 LAN0 card device ref pcie_rp11 on # Enable SSD Card PCIE 11 using clk 7 register "pcie_rp[PCH_RP(11)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/79292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Gerrit-Change-Number: 79292 Gerrit-PatchSet: 11 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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