coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/rex: Simplify power limit configuration usage
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79331?usp=email ) Change subject: mb/google/rex: Simplify power limit configuration usage ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > looks like u landed the patches out of order i have landed the base cl to fix the problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/79331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Gerrit-Change-Number: 79331 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Dec 2023 18:07:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expecta...
by Subrata Banik (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Paul Menzel, Sukumar Ghorai, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79386?usp=email ) Change subject: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Configuring MSR 0x774 is applicable to all SoC variants. > - today EPP is overwrite by OS and irrespective of any vale configured by bios/coreboot. > - hence required OS changes not to overwrite the EPP when configured by bios, as in b:314275133 : need to apply the kernel change to test this coreboot change: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/… Do you wish to land the kernel changes on priority to enable the CB changes. Also, can you please capture in the commit msg that you need a kernel patch as well to let coreboot changes take the effect ? -- To view, visit https://review.coreboot.org/c/coreboot/+/79386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Gerrit-Change-Number: 79386 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 18:04:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79116?usp=email ) Change subject: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards ...................................................................... nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/pcie.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index ec737a2..96fb12f 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <assert.h> -#if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { assert(dev); @@ -41,7 +40,6 @@ return NULL; } -#endif static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, @@ -51,9 +49,7 @@ .reset_bus = pci_bus_reset, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, -#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, -#endif }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Gerrit-Change-Number: 79116 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79367?usp=email ) Change subject: ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case ...................................................................... ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case Building the Lenovo T60/T60p, iasl 20230628 shows the remark below: dsdt.asl 2099: PowerResource (FPwR, 0, 0) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) dsdt.asl 2118: Name (_PR0, Package () { FPwR }) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) Address it by making it all upper case. Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26 Fixes: 3ab13a8691cb ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/lenovo/h8/acpi/thermal.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 4f3b76e..fa5a282 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -97,7 +97,7 @@ Name (_AL0, Package () { FAN }) - PowerResource (FPwR, 0, 0) + PowerResource (FPWR, 0, 0) { /* * WINDOWS BUG: Don't read from EmbeddedControl @@ -127,7 +127,7 @@ Device (FAN) { Name (_HID, EISAID ("PNP0C0B")) - Name (_PR0, Package () { FPwR }) + Name (_PR0, Package () { FPWR }) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/79367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26 Gerrit-Change-Number: 79367 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expecta...
by Sukumar Ghorai (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79386?usp=email ) Change subject: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > > Do this recommendation only applicable for QS silicon ? […] Configuring MSR 0x774 is applicable to all SoC variants. - today EPP is overwrite by OS and irrespective of any vale configured by bios/coreboot. - hence required OS changes not to overwrite the EPP when configured by bios, as in b:314275133 : need to apply the kernel change to test this coreboot change: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/… -- To view, visit https://review.coreboot.org/c/coreboot/+/79386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Gerrit-Change-Number: 79386 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 17:52:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79394?usp=email ) Change subject: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults ...................................................................... Abandoned not sure how i managed to do this, but when i pushed this patch the first time, i got a timeout, and then i pushed again and now there's both this patch and CB:79395 which both have the same change ID o_O -- To view, visit https://review.coreboot.org/c/coreboot/+/79394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a Gerrit-Change-Number: 79394 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79395?usp=email ) Change subject: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults ...................................................................... soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults Add defaults for the CONSOLE_UART_BASE_ADDRESS Kconfig symbol so that the SeaBIOS payload will know where the MMIO address of the UART is to build successfully without any additional user input during the build. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a --- M src/soc/amd/genoa/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/79395/1 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index a98e634..2068c44 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -163,6 +163,13 @@ See #57299 (NDA) for additional bit definitions. endmenu +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedce000 if UART_FOR_CONSOLE = 2 + config SMM_TSEG_SIZE hex default 0x800000 -- To view, visit https://review.coreboot.org/c/coreboot/+/79395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a Gerrit-Change-Number: 79395 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
by Tim Wawrzynczak (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79393?usp=email ) Change subject: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Gerrit-Change-Number: 79393 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Dec 2023 17:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Shelley Chen (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79392?usp=email ) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brox/variants/brox/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/79392/comment/e45e1de2_8e667032 : PS1, Line 4: /tmp/go-build3467193440/b001/exe/part_id_gen same here File src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt: https://review.coreboot.org/c/coreboot/+/79392/comment/fcaf33de_8c5cb91d : PS1, Line 4: /tmp/go-build3467193440/b001/exe/part_id_gen Did you use a local copy of the script? I'd rather keep the path to the common script in the repo so that the message is helpful to everyone. Any chance that you can regenerate with the common script to fix this comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 17:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
by Felix Held (Code Review) 04 Dec '23

04 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79393?usp=email ) Change subject: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print ...................................................................... acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print While acpidump_print shouldn't be called with a NULL pointer as table_ptr argument, better add a check to not end up dereferencing the NULL pointer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/79393/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e40d4ac..c4d55ab 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1367,6 +1367,8 @@ static void acpidump_print(void *table_ptr) { + if (table_ptr == NULL) + return; const acpi_header_t *header = (acpi_header_t *)table_ptr; const size_t table_size = header->length; printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature); -- To view, visit https://review.coreboot.org/c/coreboot/+/79393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Gerrit-Change-Number: 79393 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit December 2023