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Change subject: acpi/acpi_gic: Add GIC ITS subtable
......................................................................
Patch Set 6:
(1 comment)
File src/acpi/acpi_gic.c:
https://review.coreboot.org/c/coreboot/+/78115/comment/57879df8_49494828 :
PS5, Line 92: &its_base
> It needs a `uintptr_t *` pointing to an array. But that could only […]
Patcset 6 has address the issue.
Verified with build & tested by booting linux kernel which properly detected ITS.
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I'd like you to reexamine a change. Please visit
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Change subject: acpi/acpi_gic: Add GIC ITS subtable
......................................................................
acpi/acpi_gic: Add GIC ITS subtable
Add support for generating GIC subtable ITS (Interrupt Translator
Service).
Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43
Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com>
---
M src/acpi/acpi_gic.c
M src/include/acpi/acpi.h
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/78115/6
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 30:
(6 comments)
File src/mainboard/dell/optiplex_9020/Kconfig:
https://review.coreboot.org/c/coreboot/+/55232/comment/39c3fde7_990e365a :
PS30, Line 22: hex
> Symbol type is not necessary as it is defined in the src/Kconfig
Done
https://review.coreboot.org/c/coreboot/+/55232/comment/b371d932_c2afeecf :
PS30, Line 26: string
> Symbol type not necessary
Done
https://review.coreboot.org/c/coreboot/+/55232/comment/cd0d05a9_3e83148f :
PS30, Line 30: string
> Symbol type not necessary
Done
File src/mainboard/dell/optiplex_9020/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/3466ff15_c4ff8dbd :
PS30, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> Should be […]
Done
File src/mainboard/dell/optiplex_9020/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/e1e95fdb_639619f7 :
PS30, Line 1: GPL-2.0-only
> CC-PDDC, see my comment on ec. […]
Done
File src/mainboard/dell/optiplex_9020/overridetree_mt.cb:
https://review.coreboot.org/c/coreboot/+/55232/comment/8eea0855_6ec59d4d :
PS30, Line 6: birdge
> bridge
Done
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
mb/dell: Add OptiPlex 7020/9020 port
The OptiPlex 7020 and 9020 use physically identical motherboards.
Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT
(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
mic inputs untested
- Ethernet: tested, works
(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
A src/mainboard/dell/optiplex_9020/Kconfig
A src/mainboard/dell/optiplex_9020/Kconfig.name
A src/mainboard/dell/optiplex_9020/Makefile.inc
A src/mainboard/dell/optiplex_9020/acpi/ec.asl
A src/mainboard/dell/optiplex_9020/acpi/platform.asl
A src/mainboard/dell/optiplex_9020/acpi/superio.asl
A src/mainboard/dell/optiplex_9020/board_info.txt
A src/mainboard/dell/optiplex_9020/bootblock.c
A src/mainboard/dell/optiplex_9020/cmos.default
A src/mainboard/dell/optiplex_9020/cmos.layout
A src/mainboard/dell/optiplex_9020/data.vbt
A src/mainboard/dell/optiplex_9020/devicetree.cb
A src/mainboard/dell/optiplex_9020/dsdt.asl
A src/mainboard/dell/optiplex_9020/gma-mainboard.ads
A src/mainboard/dell/optiplex_9020/gpio.c
A src/mainboard/dell/optiplex_9020/hda_verb.c
A src/mainboard/dell/optiplex_9020/mainboard.c
A src/mainboard/dell/optiplex_9020/overridetree_mt.cb
A src/mainboard/dell/optiplex_9020/romstage.c
19 files changed, 698 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/55232/31
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Change subject: mb/google/brox: Generate RAM IDs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt:
https://review.coreboot.org/c/coreboot/+/79392/comment/676db120_6b019db3 :
PS1, Line 4: /tmp/go-build3467193440/b001/exe/part_id_gen
> Did you use a local copy of the script? I'd rather keep the path to the common script in the repo s […]
I think Ivy ran `go run util/spd_tools/src/part_id_gen/part_id_gen.go ADL lp5 ...`
That is why the exe was built into tmp path and executed from there.
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Change subject: soc/intel/common,mtl: Refactor BERT generation flow for crashlog
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS4:
> Please verify these changes on an ADL device.
This CL is verified and working as expected on RPL-based device. Its verified now. We had to set RESOURCE_ALLOCATION_TOP_DOWN=N, as keeping it Y makes crashlog nonfunctional. Debugging of issue(s) related to RESOURCE_ALLOCATION_TOP_DOWN can be done independently. I would recommend merging this CL.
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Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
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Change subject: mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation
......................................................................
mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation
The default EPP is set at 50%, which is deemed insufficiently
aggressive for meeting the MTL performance expectations in
balance_performance mode.
# cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
balance_performance
# iotools rdmsr 0 0x774
0x0000000080003f06
EPP=45% is giving the required performance in MTL.
# iotools rdmsr 0 0x774
0x0000000073003d06
NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932
BUG=b:314275133
TEST=Build and boot.
Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79386/5
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Change subject: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults
......................................................................
Patch Set 1: Code-Review+2
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