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[M] Change in coreboot[main]: soc/amd/*/chipset.cb: don't call dummy device functions host bridges
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nico Huber, Varshit Pandya. Hello Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nico Huber, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79396?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: soc/amd/*/chipset.cb: don't call dummy device functions host bridges ...................................................................... soc/amd/*/chipset.cb: don't call dummy device functions host bridges Function 0 of the devices that have the bridges to other buses are dummy functions that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on those devices isn't enabled. Those dummy device functions are however not PCI host bridges, so change the comments from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/genoa/chipset.cb M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/phoenix/chipset.cb M src/soc/amd/picasso/chipset.cb M src/soc/amd/stoneyridge/chipset_cz.cb M src/soc/amd/stoneyridge/chipset_st.cb 9 files changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/79396/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Gerrit-Change-Number: 79396 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/variants/deku: Enable CNVi PCI device
by Eran Mitrani (Code Review) 05 Dec '23

05 Dec '23

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79398?usp=email ) Change subject: mb/google/rex/variants/deku: Enable CNVi PCI device ...................................................................... mb/google/rex/variants/deku: Enable CNVi PCI device BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/79398/1 diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 86a015cf..9c35338 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -250,6 +250,14 @@ end end end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/79398?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Gerrit-Change-Number: 79398 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/*/chipset.cb: don't call dummy bridges host bridges
by Nico Huber (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79396?usp=email ) Change subject: soc/amd/*/chipset.cb: don't call dummy bridges host bridges ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79396/comment/ec6edc21_b4f7f4a6 : PS1, Line 10: function function*s* Patchset: PS1: TBH, I would also not call them bridges. If it really serves no other purpose than having a function 0, I would just call it "dummy" or "dummy device". -- To view, visit https://review.coreboot.org/c/coreboot/+/79396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Gerrit-Change-Number: 79396 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Dec 2023 23:47:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/amd/pi/00730F01/chipset.cb: don't call dummy bridges host bridges
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79397?usp=email ) Change subject: nb/amd/pi/00730F01/chipset.cb: don't call dummy bridges host bridges ...................................................................... nb/amd/pi/00730F01/chipset.cb: don't call dummy bridges host bridges Function 0 of the device that has the bridges to other buses is a dummy function that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on that device isn't enabled. That dummy bridge is however not a PCI host bridge, so remove the 'Host' from the dummy bridge comment. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a --- M src/northbridge/amd/pi/00730F01/chipset.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/79397/1 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index bc79426..56a6399 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -11,7 +11,7 @@ device pci 0.2 alias iommu off end device pci 1.0 alias gfx off end device pci 1.1 alias gfx_hda off end - device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.0 on end # Dummy Bridge, do not disable device pci 2.1 alias gpp_bridge_0 off end device pci 2.2 alias gpp_bridge_1 off end device pci 2.3 alias gpp_bridge_2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/79397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a Gerrit-Change-Number: 79397 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/*/chipset.cb: don't call dummy bridges host bridges
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79396?usp=email ) Change subject: soc/amd/*/chipset.cb: don't call dummy bridges host bridges ...................................................................... soc/amd/*/chipset.cb: don't call dummy bridges host bridges Function 0 of the devices that have the bridges to other buses are dummy function that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on those devices isn't enabled. Those dummy bridges are however not PCI host bridges, so remove the 'Host' from the dummy bridge comments. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/genoa/chipset.cb M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/phoenix/chipset.cb M src/soc/amd/picasso/chipset.cb M src/soc/amd/stoneyridge/chipset_cz.cb M src/soc/amd/stoneyridge/chipset_st.cb 9 files changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/79396/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 0762ea1..6c51044 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -7,12 +7,12 @@ device pci 00.0 alias gnb on ops cezanne_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_gfx_bridge_0 off ops amd_external_pcie_gpp_ops end device pci 01.2 alias gpp_gfx_bridge_1 off ops amd_external_pcie_gpp_ops end device pci 01.3 alias gpp_gfx_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end @@ -21,7 +21,7 @@ device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 0f543e7..db1682c 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -9,7 +9,7 @@ device pci 00.2 alias iommu_0 on ops amd_iommu_ops end device pci 00.3 alias rcec_0 off end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_bridge_0_0_a off end device pci 01.2 alias gpp_bridge_0_1_a off end device pci 01.3 alias gpp_bridge_0_2_a off end @@ -18,11 +18,11 @@ device pci 01.6 alias gpp_bridge_0_5_a off end device pci 01.7 alias gpp_bridge_0_6_a off end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0_7_a off end device pci 02.2 alias gpp_bridge_0_8_a off end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias gpp_bridge_0_0_b off end device pci 03.2 alias gpp_bridge_0_1_b off end device pci 03.3 alias gpp_bridge_0_2_b off end @@ -31,17 +31,17 @@ device pci 03.6 alias gpp_bridge_0_5_b off end device pci 03.7 alias gpp_bridge_0_6_b off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy Bridge, do not disable device pci 04.1 alias gpp_bridge_0_7_b off end device pci 04.2 alias gpp_bridge_0_8_b off end - device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.0 on end # Dummy Bridge, do not disable device pci 05.1 alias gpp_bridge_0_0_c off end device pci 05.2 alias gpp_bridge_0_1_c off end device pci 05.3 alias gpp_bridge_0_2_c off end device pci 05.4 alias gpp_bridge_0_3_c off end - device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.0 on end # Dummy Bridge, do not disable device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 device pci 0.0 off end # Dummy PCIe function device pci 0.1 off end @@ -77,7 +77,7 @@ device pci 00.2 alias iommu_1 on ops amd_iommu_ops end device pci 00.3 alias rcec_1 off end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_bridge_1_0_a off end device pci 01.2 alias gpp_bridge_1_1_a off end device pci 01.3 alias gpp_bridge_1_2_a off end @@ -86,11 +86,11 @@ device pci 01.6 alias gpp_bridge_1_5_a off end device pci 01.7 alias gpp_bridge_1_6_a off end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_1_7_a off end device pci 02.2 alias gpp_bridge_1_8_a off end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias gpp_bridge_1_0_b off end device pci 03.2 alias gpp_bridge_1_1_b off end device pci 03.3 alias gpp_bridge_1_2_b off end @@ -99,13 +99,13 @@ device pci 03.6 alias gpp_bridge_1_5_b off end device pci 03.7 alias gpp_bridge_1_6_b off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy Bridge, do not disable device pci 04.1 alias gpp_bridge_1_7_b off end device pci 04.2 alias gpp_bridge_1_8_b off end - device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.0 on end # Dummy Bridge, do not disable - device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.0 on end # Dummy Bridge, do not disable device pci 07.1 alias gpp_bridge_1_a off device pci 0.0 off end # Dummy PCIe function device pci 0.1 off end #SDXI @@ -118,7 +118,7 @@ device pci 00.2 alias iommu_2 on ops amd_iommu_ops end device pci 00.3 alias rcec_2 off end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_bridge_2_0_a off end device pci 01.2 alias gpp_bridge_2_1_a off end device pci 01.3 alias gpp_bridge_2_2_a off end @@ -127,11 +127,11 @@ device pci 01.6 alias gpp_bridge_2_5_a off end device pci 01.7 alias gpp_bridge_2_6_a off end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_2_7_a off end device pci 02.2 alias gpp_bridge_2_8_a off end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias gpp_bridge_2_0_b off end device pci 03.2 alias gpp_bridge_2_1_b off end device pci 03.3 alias gpp_bridge_2_2_b off end @@ -140,13 +140,13 @@ device pci 03.6 alias gpp_bridge_2_5_b off end device pci 03.7 alias gpp_bridge_2_6_b off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy Bridge, do not disable device pci 04.1 alias gpp_bridge_2_7_b off end device pci 04.2 alias gpp_bridge_2_8_b off end - device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.0 on end # Dummy Bridge, do not disable - device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.0 on end # Dummy Bridge, do not disable device pci 07.1 alias gpp_bridge_2_a off device pci 0.0 off end # Dummy PCIe function device pci 0.1 off end @@ -159,7 +159,7 @@ device pci 00.2 alias iommu_3 on ops amd_iommu_ops end device pci 00.3 alias rcec_3 off end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_bridge_3_0_a off end device pci 01.2 alias gpp_bridge_3_1_a off end device pci 01.3 alias gpp_bridge_3_2_a off end @@ -168,11 +168,11 @@ device pci 01.6 alias gpp_bridge_3_5_a off end device pci 01.7 alias gpp_bridge_3_6_a off end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_3_7_a off end device pci 02.2 alias gpp_bridge_3_8_a off end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias gpp_bridge_3_0_b off end device pci 03.2 alias gpp_bridge_3_1_b off end device pci 03.3 alias gpp_bridge_3_2_b off end @@ -181,17 +181,17 @@ device pci 03.6 alias gpp_bridge_3_5_b off end device pci 03.7 alias gpp_bridge_3_6_b off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy Bridge, do not disable device pci 04.1 alias gpp_bridge_3_7_b off end device pci 04.2 alias gpp_bridge_3_8_b off end - device pci 05.0 on end # Dummy Host Bridge, do not disable + device pci 05.0 on end # Dummy Bridge, do not disable device pci 05.1 alias gpp_bridge_3_0_c off end device pci 05.2 alias gpp_bridge_3_1_c off end device pci 05.3 alias gpp_bridge_3_2_c off end device pci 05.4 alias gpp_bridge_3_3_c off end - device pci 07.0 on end # Dummy Host Bridge, do not disable + device pci 07.0 on end # Dummy Bridge, do not disable device pci 07.1 alias gpp_bridge_3_a off device pci 0.0 off end # Dummy PCIe function device pci 0.1 off end #SDXI diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index bf7d67d..9560ee3 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -9,9 +9,9 @@ device pci 00.0 alias gnb on ops glinda_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge + device pci 01.0 on end # Dummy Bridge - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end @@ -19,7 +19,7 @@ device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index e40124f..8f88c42 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -7,15 +7,15 @@ device pci 00.0 alias gnb on ops mendocino_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge + device pci 01.0 on end # Dummy Bridge - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 394f057..d788cd8 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -7,9 +7,9 @@ device pci 00.0 alias gnb on ops mendocino_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge + device pci 01.0 on end # Dummy Bridge - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end @@ -17,7 +17,7 @@ device pci 02.5 alias gpp_bridge_4 hidden ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 12bb2fe..f87ced1 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -9,14 +9,14 @@ device pci 00.0 alias gnb on ops phoenix_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end @@ -25,13 +25,13 @@ device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias usb4_pcie_bridge_0 off end - device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.0 on end # Dummy Bridge, do not disable device pci 04.1 alias usb4_pcie_bridge_1 off end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index ed54563..d5c17a1 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -8,7 +8,7 @@ ops picasso_pci_domain_ops device pci 00.0 alias gnb on ops picasso_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.0 on end # Dummy Bridge, do not disable device pci 01.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end device pci 01.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end device pci 01.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end @@ -16,7 +16,7 @@ device pci 01.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end - device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.0 on end # Dummy Bridge, do not disable device pci 08.1 alias internal_bridge_a off # internal bridge to bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU diff --git a/src/soc/amd/stoneyridge/chipset_cz.cb b/src/soc/amd/stoneyridge/chipset_cz.cb index 1122ae8..f74527b 100644 --- a/src/soc/amd/stoneyridge/chipset_cz.cb +++ b/src/soc/amd/stoneyridge/chipset_cz.cb @@ -10,13 +10,13 @@ device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 01.1 alias gfx_hda off end # display HD Audio controller - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off end device pci 02.2 alias gpp_bridge_1 off end device pci 02.3 alias gpp_bridge_2 off end device pci 02.4 alias gpp_bridge_3 off end device pci 02.5 alias gpp_bridge_4 off end - device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.0 on end # Dummy Bridge, do not disable device pci 03.1 alias gfx_bridge_0 off end device pci 03.2 alias gfx_bridge_1 off end device pci 03.3 alias gfx_bridge_2 off end diff --git a/src/soc/amd/stoneyridge/chipset_st.cb b/src/soc/amd/stoneyridge/chipset_st.cb index fd148a8..8015e36 100644 --- a/src/soc/amd/stoneyridge/chipset_st.cb +++ b/src/soc/amd/stoneyridge/chipset_st.cb @@ -10,7 +10,7 @@ device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 01.1 alias gfx_hda off end # display HD Audio controller - device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.0 on end # Dummy Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off end device pci 02.2 alias gpp_bridge_1 off end device pci 02.3 alias gpp_bridge_2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/79396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Gerrit-Change-Number: 79396 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/78327/comment/458863f0_7f6e8bb9 : PS4, Line 112: .scan_bus = non_iio_pci_domain_scan_bus, > Don't these integrated devices implement the upper layers of PCI (i.e. show as a […] yeah ... integrated_iio_stack_... is a good idea. P.S. these devices are integrated and logically PCI devices, but there is no physical PCI PHY between them and the core. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 04 Dec 2023 23:21:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: acpi: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Naresh Solanki, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Hello Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77884?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: acpi: Add IO Remapping Table structures ...................................................................... acpi: Add IO Remapping Table structures Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h A src/include/acpi/acpi_iort.h 4 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/77884/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: acpi: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77884?usp=email ) Change subject: acpi: Add IO Remapping Table structures ...................................................................... Patch Set 8: (1 comment) Commit Message: PS6: > Had some difficulty booting with all latest table revision with Fedora36 linux kernel 5.15 . […] Have aligned with ARM DEN 0049E.e & test for successful boot in linux kernel 6.6 -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Dec 2023 22:16:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: acpi: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 04 Dec '23

04 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Hello Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77884?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: acpi: Add IO Remapping Table structures ...................................................................... acpi: Add IO Remapping Table structures Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h A src/include/acpi/acpi_iort.h 4 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/77884/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
by Paul Menzel (Code Review) 04 Dec '23

04 Dec '23

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79116?usp=email ) Change subject: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Why are those unneeded? -- To view, visit https://review.coreboot.org/c/coreboot/+/79116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Gerrit-Change-Number: 79116 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Dec 2023 22:07:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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