coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
by Deepti Deshatty (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Kapil Porwal, Krishna P Bhat D, Paul Menzel, Subrata Banik. Hello Balaji Manigandan, Deepti Deshatty, Kapil Porwal, Krishna P Bhat D, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79209?usp=email to look at the new patch set (#6). Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region ...................................................................... mb/intel/mtlrvp: add 512KB SI_EC FMAP region This patch introduces the 512KB SI_EC FMAP region for storing the EC firmware, a necessary addition to support EC chips without internal flash memory. As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction with the Microchip EC1723, and the changes are verified. Cq-Depend: chrome-internal: 6691498 Cq-Depend: chrome-internal: 6741356 BUG=b:289783489 TEST=build "emerge-rex coreboot chromeos-bootimage" is successful Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 6 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
by Patrick Rudolph (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79167?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Gerrit-Change-Number: 79167 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 09:31:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree
by Patrick Rudolph (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79171?usp=email ) Change subject: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Gerrit-Change-Number: 79171 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 09:31:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults
by Varshit Pandya (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Felix Held, Martin L Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79395?usp=email ) Change subject: soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: please add the topic 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/79395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a Gerrit-Change-Number: 79395 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Dec 2023 03:23:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 05 Dec '23

05 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating the GPIOs needing to be initialized in romstage into the baseboard gpio.c file. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c M src/mainboard/google/brox/variants/brox/gpio.c 3 files changed, 59 insertions(+), 58 deletions(-) Approvals: Ivy Jian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index a909533..841da6f 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -393,21 +393,36 @@ PAD_CFG_GPI(GPP_S0, NONE, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), +}; + const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } +const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_WEAK_CROS_GPIOS(cros_gpios); - -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c index bcad9b4..dabb653 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c @@ -5,65 +5,64 @@ #include <gpio.h> static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP4X, + .type = MEM_TYPE_LP5X, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = {40, 30, 30, 30, 30}, - }, + /* Leave Rcomp unspecified to use the FSP optimized defaults */ /* DQ byte map */ .lpx_dq_map = { .ddr0 = { - .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, - .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, }, + .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, }, }, .ddr1 = { - .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr2 = { - .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, - .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, }, + .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, }, }, .ddr3 = { - .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, - .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, }, + .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, }, }, .ddr4 = { - .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, - .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, }, + .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, }, }, .ddr5 = { - .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, - .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr6 = { - .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, - .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, }, + .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, }, }, .ddr7 = { - .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, - .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, }, + .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, }, }, }, /* DQS CPU<>DRAM map */ .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = 1, /* Enable Early Command Training */ + .lp5x_config = { + .ccc_config = 0x99, + }, + + .ect = 1, /* Early Command Training */ + }; const struct mb_cfg *__weak variant_memory_params(void) @@ -75,16 +74,16 @@ { /* * Memory configuration board straps - * GPIO_MEM_CONFIG_0 GPP_E11 - * GPIO_MEM_CONFIG_1 GPP_E2 - * GPIO_MEM_CONFIG_2 GPP_E1 - * GPIO_MEM_CONFIG_3 GPP_E12 + * MEM_STRAP_0 GPP_E15 + * MEM_STRAP_1 GPP_E12 + * MEM_STRAP_2 GPP_E13 + * MEM_STRAP_3 GPP_E10 */ gpio_t spd_gpios[] = { - GPP_E11, - GPP_E2, - GPP_E1, + GPP_E15, GPP_E12, + GPP_E13, + GPP_E10, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); @@ -92,8 +91,8 @@ bool __weak variant_is_half_populated(void) { - /* GPIO_MEM_CH_SEL GPP_E13 */ - return gpio_get(GPP_E13); + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); } void __weak variant_get_spd_info(struct mem_spd *spd_info) diff --git a/src/mainboard/google/brox/variants/brox/gpio.c b/src/mainboard/google/brox/variants/brox/gpio.c index 5805bee..5af3552 100644 --- a/src/mainboard/google/brox/variants/brox/gpio.c +++ b/src/mainboard/google/brox/variants/brox/gpio.c @@ -4,21 +4,8 @@ #include <boardid.h> #include <soc/gpio.h> - -static const struct pad_config romstage_gpio_table[] = { - - /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_F9, 1, DEEP), -}; - const struct pad_config *variant_gpio_override_table(size_t *num) { *num = 0; return NULL; } - -const struct pad_config *variant_romstage_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Shelley Chen (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79392?usp=email ) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 01:50:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Ivy Jian (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79392?usp=email ) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/brox/variants/brox/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/79392/comment/d74a094e_a2ed502a : PS1, Line 4: /tmp/go-build3467193440/b001/exe/part_id_gen > same here Thanks for the reminder, I regenerated it by './util/spd_tools/bin/part_id_gen ADL lp5 ...'. File src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt: https://review.coreboot.org/c/coreboot/+/79392/comment/1a365fe2_130f9ddf : PS1, Line 4: /tmp/go-build3467193440/b001/exe/part_id_gen > I think Ivy ran `go run util/spd_tools/src/part_id_gen/part_id_gen.go ADL lp5 ...` […] Thanks for the reminder, I regenerated it by './util/spd_tools/bin/part_id_gen ADL lp5 ...'. -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 00:58:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Generate RAM IDs
by Ivy Jian (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Ivy Jian, Shelley Chen. Hello Karthik Ramasubramanian, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79392?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Generate RAM IDs ...................................................................... mb/google/brox: Generate RAM IDs Add the support LP5 RAM parts for brox: DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/brox/memory/Makefile.inc M src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt M src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79392/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib17f26a310435e37088191594863a645aa751440 Gerrit-Change-Number: 79392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd/*/chipset.cb: don't call dummy device functions host bridges
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nico Huber, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79396?usp=email ) Change subject: soc/amd/*/chipset.cb: don't call dummy device functions host bridges ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79396/comment/21353c6d_2acfc7d6 : PS1, Line 10: function > function*s* Done Patchset: PS1: > TBH, I would also not call them bridges. If it really serves no other […] good point; updated the patches -- To view, visit https://review.coreboot.org/c/coreboot/+/79396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Gerrit-Change-Number: 79396 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Dec 2023 00:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge
by Felix Held (Code Review) 05 Dec '23

05 Dec '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79397?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge ...................................................................... nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge Function 0 of the device that has the bridges to other buses is a dummy function that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on that device isn't enabled. That dummy device function is however not a PCI host bridge, so change the comment from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a --- M src/northbridge/amd/pi/00730F01/chipset.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/79397/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a Gerrit-Change-Number: 79397 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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